Toshiba TX49 TMPR4937, Manual

Page: 234 / 553

Chapter 9 SDRAM Controller
9-18
9.4.1 SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0)
0x8008 (ch. 1)
0x8010 (ch. 2)
0x8018 (ch. 3)
When the SDCCRn is programmed using a sequence of 32-bit store instructions, the base address and
the address mask in the high-order 32-bit portion of the register must be written first, followed by the
Channel Enable bit in the low-order 32-bit portion.
63 49 48
BA
Reserved
R/W :Type
0x01FC/0x0000 :Initial value
47 33 32
AM
Reserved
R/W :Type
0x0000 :Initial value
31 29 28 16
ECC Reserved
R/W :Type
0 0 0 :Initial value
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD MT
Reserved
ME SE CE
Reserved
BS
Reserved
RS CS
Reserved
MW
R/W R/W R/W R/W R/W R/W R/W R/W R/W :Type
0 0
1)
0 0 0
1)
0 000
1)
000
1)
1 :Initial value
Bit Mnemonic Field Name Description Read/Write
63:49 BA[35:21] Base Address Base Address (Default: 0x01FC/0x0000)
Specifies the base address. The upper 15 bits [35:21] of the physical
address are compared to the value of this field.
(Note) Only the default for Channel 0 differs. Channel 0: 0x01FC, Others:
0x0000 R/W
48 — — Reserved
⎯
47:33 AM[35:21] Address Mask Address Mask (Default: 0x0000)
Sets the valid bits for address comparison according to the base address.
0: Bits of the corresponding BA field are compared.
1: Bits of the corresponding BA field are not compared. R/W
32 — — Reserved
⎯
31:29 ECC ECC/Parity Mode ECC/Parity mode (Default: 000)
Specifies the channel ECC/Parity type (refer to 9.3.10.1).
000: NOP Mode
001: EC Mode
010: ECC Mode
011: ECC + scrub Mode
100: Even Parity Mode
101: Odd Parity Mode
110: Reserved
110: Reserved
R/W
28:16 — — Reserved
⎯
Figure 9.4.1 SDRAM Channel Control Register (1/2)