Toshiba TX49 TMPR4937, Manual

Page: 353 / 553

Chapter 10 PCI Controller
10-95
10.4.63 PDMAC Status Register (PDMSTATUS) 0xD228
63 48
Reserved
: Type
: Initial value
47 32
Reserved
: Type
: Initial value
31 30 29 24 23 20 19 18 17 16
Reserved REQCNT FIFOCNT FIFOWP FIFORP
R R R R : Type
0x00 0x0 0x0 0x0 : Initial value
15 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ERRINT
DONEINT
CHNEN
XFRACT
ACCMP NCCMP NTCMP
Reserved
CFGERR
PCIERR
CHNERR
DATAERR
R R R R R R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C : Type
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 : Initial value
Bit Mnemonic Field Name Description Read/Write
63:30 Reserved
⎯
29:24 REQCNT Request Delay
Time Counter
Request Delay Counter (Default: 0x00)
This field indicates the request delay time counter value as 16
×
n
when the
6-bit value of this field is
n
.
R
23:20 FIFOCNT FIFO Hold Count FIFO Valid Entry Count (Default: 0x0)
This field indicates the number of bytes that was written in the FIFO but not
yet read. This is a diagnostic function.
R
19:18 FIFOWP FIFO Write
Pointer
FIFO Write Pointer (Default: 0x0)
This field indicates the next Write position in the FIFO. This is a diagnostic
function. R
17:16 FIFORP FIFO Read
Pointer
FIFO Read Pointer (Default: 0x0)
This field indicates the next Read position in the FIFO. This is a dianostic
function. R
15:12 Reserved
⎯
11 ERRINT
Error Interrupt
Status
Error Interrupt Status (Default: 0x0)
Indicates whether to signal an error interrupt.
1: An error interrupt request exists.
0: No error interrupt request exists. R
10 DONEINT Normal Transfer
Complete
Interrupt Status Normal Transfer Complete Interrupt Status (Default: 0x0)
Indicates whether a Normal Transfer Complete Interrupt is signaled.
This bit becomes “1” when either the Normal Chain Complete bit (NCCMP)
is set and the Normal Chain Complete Interrupt Enable bit (NCCMPIE) is
set, or when the Normal Data Transfer Complete bit (NTCMP) is set and
the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) is set.
1: A Normal Transfer Complete Interrupt request exists.
0: No Normal Transfer Complete Interrupt request exists. R
9 CHNEN Chain Enable Chain Enable (Default: 0x0)
This bit is a copy of the Chain Enable bit in the PDMAC Configuration
Register. R
Figure 10.4.61 Status Register (1/2)