Chapter 11 Serial I/O Port
11-21
11.4.6 Flow Control Register 0 (SIFLCR0)
0xF314 (Ch. 0)
Flow Control Register 1 (SIFLCR1)
0xF414 (Ch. 1)
31
16
Reserved
:
Type
:
Initial
value
15 13 12 11 10 9 8 7 6 5 4 1 0
Reserved RCS
TES
Reserved
RTSSC
RSDE TSDE
Reserved RTSTL
TBRK
R/W
R/W R/W
R/W
R/W
R/W
R/W
:
Type
0 0 0 1 1
0001
0
:
Initial
value
Bit Mnemonic Field
Name
Description
Read/Write
31:13 Reserved
⎯
12 RCS
RTS Signal
Control Select
RTS Control Select (Default: 0)
This field sets the reception flow control using RTS output signals.
0: Disable flow control using RTS signals.
1: Enable flow control using RTS signals.
R/W
11 TES
CTS Signal
Control Select
CTS Control Select (Default: 0)
This field sets the transmission flow control using CTS input signals.
0: Disable flow control using CTS signals.
1: Enable flow control using CTS signals.
R/W
10
Reserved
⎯
9 RTSSC
RTS Software
Control
RTS Software Control (Default: 0)
This register is used for software control of RTS output signals.
0: Set the RTS signal to Low (can receive data).
1: Sets the RTS signal to High (transmission pause request)
R/W
8 RSDE
Serial Data
Reception
Disable
Receive Serial Data Disable (Default: 1)
This is the Serial Data Disable bit. When this bit is cleared, data reception
starts after the start bit is detected. The RTS signal will not become High
even if this bit is cleared.
0: Enable (can receive data)
1: Disable (halt reception)
R/W
7 TSDE
Serial Data
Transmit Disable
Transmit Serial Data Disable (Default: 1)
This is the Serial Data Transmission Disable bit. When this bit is cleared,
data transmission starts. When set, transmission stops after completing
transmission of the current frame.
0: Enable (can transmit data)
1: Disable (halt transmission)
R/W
6:5 Reserved
⎯
4:1 RTSTL
RTS Active
Trigger Level
RTS Trigger Level (Default: 0001)
The RTS hardware control assert level is set by the reception data stage
count of the Receive FIFO.
0000: Disable setting
0001: 1
:
1111: 15
R/W
0 TBRK
Break
Transmission
Break Transmit (Default: 0)
Transmits a break. The TXD signal is Low while TBRK is set to “1”.
0: Disable (clear break)
1: Enable (transmit break)
R/W
Figure 11.4.6 Flow Control Register
Summary of Contents for TX49 TMPR4937
Page 1: ...64 Bit TX System RISC TX49 Family TMPR4937 Rev 2 0 ...
Page 4: ......
Page 13: ...Table of Contents ix TMPR4937 Revision History 1 ...
Page 14: ...Table of Contents x ...
Page 15: ...Handling Precautions ...
Page 16: ......
Page 18: ...1 Using Toshiba Semiconductors Safely 1 2 ...
Page 40: ...3 General Safety Precautions and Usage Considerations 3 18 ...
Page 42: ...4 Precautions and Usage Considerations 4 2 ...
Page 43: ...TMPR4937 2005 3 Rev 2 0 ...
Page 44: ......
Page 52: ...Chapter 1 Overview and Features 1 6 ...
Page 156: ...Chapter 7 External Bus Controller 7 56 ...
Page 491: ...Chapter 16 Removed 16 1 16 Removed ...
Page 492: ...Chapter 16 Removed 16 2 ...
Page 493: ...Chapter 17 Removed 17 1 17 Removed ...
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Page 497: ...Chapter 19 Removed 19 1 19 Removed ...
Page 498: ...Chapter 19 Removed 19 2 ...
Page 506: ...Chapter 20 Extended EJTAG Interface 20 8 ...
Page 530: ...Chapter 22 Pinout and Package Information 22 10 ...
Page 542: ...Chapter 24 Parts Number when Ordering 24 2 ...