Toshiba TX49 TMPR4937, Manual

Page: 338 / 553

Chapter 10 PCI Controller
10-80
10.4.49 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0xD198
63 48
Reserved
: Type
: Initial value
47 39 38 37 36 35 32
Reserved
P2GIOEN
BSWAP
EXFER BA[35:32]
R/W R/W R/W R/W : Type
0x0
0x0/0x1 0x1/0x0
0x0 : Initial value
31 16
BA[31:16]
R/W : Type
0x0000 : Initial value
15 8 7 0
BA[15:8] Reserved
R/W : Type
0x00 : Initial value
Bit Mnemonic Field Name Description Read/Write
63:39 Reserved
⎯
38 P2GIOEN I/O Space Enable Target I/O Space Enable (Default: 0x0) Controls whether the I/O Space for
target access is valid or invalid.
When this bit is set to invalid, Writes to the I/O Space Base Address
Register of the PCI Configuration Register become invalid. Also, “0” is
returned to Reads as a response.
1: Validates I/O Space for target access.
0: Invalidates I/O Space for target access.
R/W
37 BSWAP Byte Swap Byte Swap Disable
(Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte
swapping of the I/O Space for target access.
1: Do not perform byte swapping.
0: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to “1”
when in the Big Endian Mode, the byte order of transfer to the I/O Space
through DWORD (32-bit) access will not change. R/W
36 EXFER Endian Transfer Endian Transfer
(Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian
Transfer of the I/O Space for target access.
1: Performs Endian Transfer.
0: Does not perform Endian Transfer.
Please use the default state. R/W
35:8 BA[35:8] Memory Space
Base Address 2
Base Address 2 (Default: 0x000)
Sets the G-Bus base bus address of the I/O Space for target access. Can
set the base address in 256-byte units. R/W
7:1 Reserved
⎯
Figure 10.4.47 P2G I/O Space G-Bus Base Address Register