Toshiba TX49 TMPR4937, Manual

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Chapter 23 Notes on Use of TMPR4937
23-9
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Restriction when Initiator Write by PDMAC and Target Read conflict.
[Restriction]
Don’t perform Target Read from a register on the G-Bus when the condition is the following
<Conditions>.
[Violation]
When an Initiator Write transaction using PDMAC (PCI Dedicated DMA Controller) mounted in the
PCI Controller of the target product and a Target Read transaction to the target product by the a device
on the PCI Bus conflict, there are cases when the Target Read data is corrupted.
<Conditions>
(1) In the PCI Controller of the above target product:
A. PDMAC performs an Initiator Write transaction to a device on the PCI Bus.
B. Device on the PCI Bus becomes the Bus Master and performs a Target Read on the target
product.
When the two above accesses conflict,
(2) The internal bus (G-Bus) of the target product is accessed continuously in the following order.
(a) PDMAC reads the Initiator Write data on the G-Bus.
(b) TC (Target Controller) reads data from the G-Bus because of a Target Read request.
(3) The target of the Target Read in (2) is a register on the G-Bus
However, there is no corresponding register on the Internal Bus (IM-Bus).
[Workarounds]
Do not perform Target Read access from a register on the G-Bus under the above conditions. The
register on the G-Bus is a register with the 0x8000 to 0xEFFF offset address.
PDMAC
TC
Device 1 on
PCI Bus
Device 2 on
PCI Bus
G-Bus
TX49
(CP0)
SDRAM
etc
SDRAMC
EBIF
PCI Bus
Memory Bus
Data
G-Bus
Module
Reg.
A. PDMAC Initiator Write
B. Target Read
(a)
(b)
TX4937