Toshiba TX49 TMPR4937, Manual

Page: 260 / 553

Chapter 10 PCI Controller
10-2
10.1.3 Target Function
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Single and Burst transfer from the PCI Bus to the Internal Bus
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Supports memory, I/O, and configuration cycles
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Supports high-speed back-to-back transactions on the PCI Bus
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Address mapping between the PCI Bus and the Internal bus can be modified
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Mounted 8-stage 64-bit data FIFO for Read
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Mounted 12-stage 64-bit data FIFO for Write
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Post Write function enables quick termination of a maximum of nine Write transactions by the PCI
Bus without waiting for completion on the G-Bus.
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Read Burst length (pre-fetch data size) on the Internal Bus when reading a pre-fetchable space can
be made programmable
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Endian switching function
10.1.4 PCI Arbiter
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Supports four external PCI bus masters
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Uses the Programmable Fairness algorithm (two levels with different priorities for four round-
robin request/grant pairs)
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Supports bus parking
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Bus master uses the Most Recently Used algorithm
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Unused slots and broken masters can be automatically disabled after Power On reset
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On-chip arbitration function can be disabled and external arbiter can be used
10.1.5 PDMAC (PCI DMA Controller)
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Direct Memory Access (DMA) Controller dedicated to 1-channel PCI
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Is possible to transfer data using minimal G-Bus bandwidth
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Data can be transferred bidirectionally between the G-Bus and the PCI Bus
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Specifying a physical address on the PCI Bus and an address on the G-Bus makes it possible to
automatically transfer data between the PCI Bus and the G-Bus
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Supports the Chain DMA mode, in which a Descriptor containing chain-shaped addresses and a
transfer size is automatically read from memory while DMA transfer continuous
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On-chip 4-stage 64-bit data buffer