Toshiba TX49 TMPR4937, Manual

Page: 9 / 553

Table of Contents
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10.4.37 G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0xD148................................. 10-65
10.4.38 G2P I/O Space Address Mask Register (G2PIOMASK) 0xD14C ............................................. 10-66
10.4.39 G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 0xD150 .......................... 10-67
10.4.40 G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 0xD158 .......................... 10-68
10.4.41 G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) 0xD160 .......................... 10-69
10.4.42 G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0xD168....................................... 10-70
10.4.43 PCI Controller Configuration Register (PCICCFG) 0xD170 .................................................... 10-71
10.4.44 PCI Controller Status Register (PCICSTATUS) 0xD174 ................................................................ 10-74
10.4.45 PCI Controller Interrupt Mask Register (PCICMASK) 0xD178 ............................................... 10-76
10.4.46 P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 0xD180 ..................... 10-77
10.4.47 P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 0xD188 ..................... 10-78
10.4.48 P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0xD190 ..................... 10-79
10.4.49 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0xD198.................................. 10-80
10.4.50 G2P Configuration Address Register(G2PCFGADRS) 0xD1A0 .............................................. 10-81
10.4.51 G2P Configuration Data Register (G2PCFGDATA) 0xD1A4 ................................................... 10-82
10.4.52 G2P Interrupt Acknowledge Data Register (G2PINTACK) 0xD1C8 ........................................ 10-83
10.4.53 G2P Special Cycle Data Register (G2PSPC) 0xD1CC.................................................................... 10-84
10.4.54 Configuration Data 0 Register (PCICDATA0) 0xD1D0.................................................................. 10-85
10.4.55 Configuration Data 1 Register (PCICDATA1) 0xD1D4.................................................................. 10-86
10.4.56 Configuration Data 2 Register (PCICDATA2) 0xD1D8.................................................................. 10-87
10.4.57 Configuration Data 3 Register (PCICDATA3) 0xD1DC ................................................................. 10-88
10.4.58 PDMAC Chain Address Register (PDMCA) 0xD200 .................................................................... 10-89
10.4.59 PDMAC G-Bus Address Register (PDMGA) 0xD208.................................................................... 10-90
10.4.60 PDMAC PCI Bus Address Register (PDMPA) 0xD210 .................................................................. 10-91
10.4.61 PDMAC Count Register (PDMCTR) 0xD218 ................................................................................ 10-92
10.4.62 PDMAC Configuration Register (PDMCFG) 0xD220.................................................................... 10-93
10.4.63 PDMAC Status Register (PDMSTATUS) 0xD228 ........................................................................ 10-95
10.5 PCI Configuration Space Register ............................................................................................................. 10-98
10.5.1 Capability ID Register (Cap_ID) 0xDC .......................................................................................... 10-99
10.5.2 Next Item Pointer Register (Next_Item_Ptr) 0xDD...................................................................... 10-100
10.5.3 Power Management Capability Register (PMC) 0xDE ................................................................. 10-101
10.5.4 Power Management Control/Status Register (PMCSR) 0xE0 ................................................. 10-102
11. Serial I/O Port ....................................................................................................................................................... 11-1
11.1 Features ........................................................................................................................................................ 11-1
11.2 Block Diagram ............................................................................................................................................. 11-2
11.3 Detailed Explanation.................................................................................................................................... 11-3
11.3.1 Overview ........................................................................................................................................... 11-3
11.3.2 Data Format ....................................................................................................................................... 11-3
11.3.3 Serial Clock Generator....................................................................................................................... 11-5
11.3.4 Data Reception................................................................................................................................... 11-7
11.3.5 Data Transmission ............................................................................................................................. 11-7
11.3.6 DMA Transfer .................................................................................................................................... 11-7
11.3.7 Flow Control...................................................................................................................................... 11-8
11.3.8 Reception Data Status ........................................................................................................................ 11-8
11.3.9 Reception Time Out ........................................................................................................................... 11-9
11.3.10 Software Reset ................................................................................................................................... 11-9
11.3.11 Error Detection/Interrupt Signaling ..................................................................................................11-10
11.3.12 Multi-Controller System ...................................................................................................................11-11
11.4 Registers......................................................................................................................................................11-12
11.4.1 Line Control Register 0 (SILCR0) 0xF300 (Ch. 0)
Line Control Register 1 (SILCR1) 0xF400 (Ch. 1) ..........................................................................11-13
11.4.2 DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0)
DMA/Interrupt Control Register 1 (SIDICR1) 0xF404 (Ch. 1)........................................................11-15
11.4.3 DMA/Interrupt Status Register 0 (SIDISR0) 0xF308 (Ch. 0)
DMA/Interrupt Status Register 1 (SIDISR1) 0xF408 (Ch. 1) ..........................................................11-17
11.4.4 Status Change Interrupt Status Register 0 (SISCISR0) 0xF30C (Ch. 0)
Status Change Interrupt Status Register 1 (SISCISR1) 0xF40C (Ch. 1) .......................................11-19