Toshiba TX49 TMPR4937, Manual

Page: 354 / 553

Chapter 10 PCI Controller
10-96
Bit Mnemonic Field Name Description Read/Write
8 XFRACT Transfer Active Transfer Active (Default: 0x0)
This bit is a copy of the Transfer Active bit in the PDMAC Configuration
Register. R
7 ACCMP Abnormal Chain
Completion Abnormal Chain Complete (Default: 0x0)
1: Indicates that the Chain transfer ended in an error state. In other words,
this reflects an OR operation of the PDMAC Status Register bits [3:0].
0: Indicates that no error has occurred in the Chain transfer since the
previous error bit was cleared.
Note: Bits [3:0] of the PDMAC Status Register must be cleared in order to
clear this bit.
R
6 NCCMP Normal Chain
Completion Normal Chain Complete (Default: 0x0)
1: Indicates that the Chain transfer ended in the Normal state.
0: Indicates that Chain transfer has not ended since this bit was previously
cleared. R/W1C
5 NTCMP Normal Data
Transfer
Complete Normal Data Transfer Complete (Default: 0x0)
1: Indicates that the data transfer specified by the PDMAC Register ended
in the Normal state.
0: Indicates that data transfer has not ended since this bit was previously
cleared.
R/W1C
4 Reserved
⎯
3 CFGERR
Configuration
Error
Configuration Error (Default: 0x0)
1: Indicates that either the current setting of the control portion in the
Control Register and the Address/Count Register are not consistent with
each other or the PDMAC stipulation is not being obeyed. DMA transfer
stops.
0: Indicates that the current setting of the control portion in the Control
Register can be tolerated.
R/W1C
2 PCIERR PCI Fatal Error PCI Fatal Error (Default: 0x0)
1: Indicates that an error was signaled on the PCI Bus during the Chain
process.
0: Indicates that no error has been signaled on the PCI Bus since this bit
was previously cleared.
R/W1C
1 CHNERR G-Bus Chain
Error G-Bus Chain Bus Error (Default: 0x0)
1: Indicates that a G-Bus error occurrred during the Chain process. DMA
transfer stops.
0: Indicates that no G-Bus error has occurred during the Chain process
since this bit was cleared.
R/W1C
0 DATAERR G-Bus Data Error G-Bus Data Bus Error (Default: 0x0)
1: Indicates that a G-Bus error occurred during the data transfer process.
DMA transfer stops.
0: Indicates that no G-Bus error has occurred during the data transfer
process since this bit was cleared.
R/W1C
Figure 10.4.61 Status Register (2/2)