Toshiba TX49 TMPR4937, Manual

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Table of Contents
iv
10.1.2 Initiator Function ............................................................................................................................... 10-1
10.1.3 Target Function .................................................................................................................................. 10-2
10.1.4 PCI Arbiter......................................................................................................................................... 10-2
10.1.5 PDMAC (PCI DMA Controller)........................................................................................................ 10-2
10.2 Block Diagram ............................................................................................................................................. 10-3
10.3 Detailed Explanation.................................................................................................................................... 10-4
10.3.1 Terminology Explanation .................................................................................................................. 10-4
10.3.2 On-chip Register ................................................................................................................................ 10-4
10.3.3 Supported PCI Bus Commands ......................................................................................................... 10-6
10.3.4 Initiator Access (G-Bus
→
PCI Bus Address Conversion) ................................................................ 10-8
10.3.5 Target Access (PCI Bus
→
G-Bus Address Conversion)................................................................. 10-10
10.3.6 Post Write Function ......................................................................................................................... 10-12
10.3.7 Endian Switching Function.............................................................................................................. 10-12
10.3.8 66 MHz Operation Mode ................................................................................................................. 10-13
10.3.9 Power Management ......................................................................................................................... 10-14
10.3.10 PDMAC (PCI DMA Controller)...................................................................................................... 10-15
10.3.11 Error Detection, Interrupt Reporting................................................................................................ 10-18
10.3.12 PCI Bus Arbiter................................................................................................................................ 10-20
10.3.13 PCI Boot .......................................................................................................................................... 10-22
10.3.14 Set Configuration Space .................................................................................................................. 10-23
10.3.15 PCI Clock ........................................................................................................................................ 10-23
10.4 PCI Controller Control Register................................................................................................................. 10-24
10.4.1 ID Register (PCIID) 0xD000 ........................................................................................................... 10-26
10.4.2 PCI Status, Command Register (PCISTATUS) 0xD004.................................................................. 10-27
10.4.3 Class Code, Revision ID Register (PCICCREV) 0xD008............................................................... 10-30
10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C......................................................................... 10-31
10.4.5 P2G Memory Space 0 PCI Lower Base Address Register (P2GM0PLBASE) 0xD010 ................ 10-32
10.4.6 P2G Memory Space 0 PCI Upper Base Address Register (P2GM0PUBASE) 0xD014 ................ 10-33
10.4.7 P2G Memory Space 1 PCI Lower Base Address Register (P2GM1PLBASE) 0xD018 ................ 10-33
10.4.8 P2G Memory Space 1 PCI Upper Base Address Register (P2GM1PUBASE) 0xD01C ................ 10-34
10.4.9 P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0xD020......................... 10-34
10.4.10 P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0xD024 ...................................... 10-35
10.4.11 Subsystem ID Register (PCISID) 0xD02C...................................................................................... 10-36
10.4.12 Capabilities Pointer Register (PCICAPPTR) 0xD034..................................................................... 10-37
10.4.13 PCI Configuration 2 Register (PCICFG2) 0xD03C......................................................................... 10-38
10.4.14 G2P Timeout Count Register (G2PTOCNT) 0xD040 .................................................................... 10-39
10.4.15 G2P Status Register (G2PSTATUS) 0xD080................................................................................... 10-40
10.4.16 G2P Interrupt Mask Register (G2PMASK) 0xD084 ....................................................................... 10-41
10.4.17 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088.................................................... 10-42
10.4.18 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C.............................................................. 10-43
10.4.19 P2G Configuration Register (P2GCFG) 0xD090 ............................................................................ 10-44
10.4.20 P2G Status Register (P2GSTATUS) 0xD094 .................................................................................. 10-46
10.4.21 P2G Interrupt Mask Register (P2GMASK) 0xD098 ....................................................................... 10-47
10.4.22 P2G Current Command Register (P2GCCMD) 0xD09C ................................................................ 10-48
10.4.23 PCI Bus Arbiter Request Port Register (PBAREQPORT) 0xD100 ........................................... 10-49
10.4.24 PCI Bus Arbiter Configuration Register (PBACFG) 0xD104 ................................................... 10-51
10.4.25 PCI Bus Arbiter Status Register (PBASTATUS) 0xD108 ............................................................... 10-52
10.4.26 PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0xD10C ............................................. 10-53
10.4.27 PCI Bus Arbiter Broken Master Register (PBABM) 0xD110 ................................................... 10-54
10.4.28 PCI Bus Arbiter Current Request Register (PBACREQ) 0xD114 ............................................. 10-55
10.4.29 PCI Bus Arbiter Current Grant Register (PBACGNT) 0xD118 ................................................ 10-56
10.4.30 PCI Bus Arbiter Current State Register (PBACSTATE) 0xD11C ............................................. 10-57
10.4.31 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0xD120 ..................... 10-59
10.4.32 G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0xD128 ..................... 10-60
10.4.33 G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0xD130 ..................... 10-61
10.4.34 G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 0xD138.................................. 10-62
10.4.35 G2P Memory Space 0 Address Mask Register (G2PM0MASK) 0xD140................................. 10-63
10.4.36 G2P Memory Space 1 Address Mask Register (G2PM1MASK) 0xD144................................. 10-64