Omron CP1L CPU UNIT - 03-2009, Operation Manual

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747
PLC Setup Appendix G
2 2-3 2-3-3 Start Code Disable. Disable. Every cycle 149
(CP1L M-
type CPU
Unit) 12 0
Set. 165
(CP1L L-
type CPU
Unit)
1
2-3-4 Start Code 00 hex0x0000 0x0000 Every cycle 148
(CP1L M-
type CPU
Unit) 08 to
15 00 hex
: :
0x00FF 164
(CP1L L-
type CPU
Unit) FF hex
2-3-5 End Code Received
Bytes: Receive
specified num-
ber of bytes. Received Bytes: Receive
specified number of
bytes. Every cycle 149
(CP1L M-
type CPU
Unit) 08 and
09 00
CR,LF 10
Set End Code 165
(CP1L L-
type CPU
Unit) 01
2-3-6 Received
Bytes 256 bytes 256 bytes Every cycle 149
(CP1L M-
type CPU
Unit) 00 to
07 00 hex
1 byte 01 hex
: :
255 bytes 165
(CP1L L-
type CPU
Unit) FF hex
2-3-7 Set End
Code 0x0000 1 byte Every cycle 148
(CP1L M-
type CPU
Unit) 00 to
07 00 hex
: :
255 bytes 164
(CP1L L-
type CPU
Unit) FF hex
2-3-8 Delay 0 ms 0: 0
×
10 ms Every cycle 146
(CP1L M-
type CPU
Unit) 00 to
15 0000 hex
: :
9999: 9999
×
10 ms 162
(CP1L L-
type CPU
Unit) 270F hex
2-4 ToolBus (peripheral bus)
2-4-1 Baud 9,600 bps 9,600 bps Every cycle 145
(CP1L M-
type CPU
Unit) 00 to
07 00 or
06 hex
19,200 bps 07 hex
38,400 bps 161
(CP1L L-
type CPU
Unit) 08 hex
57,600 bps 09 hex
115,200 bps 0A hex
Name Default Settings When setting is read
by CPU Unit
Internal
address
Bits Settings