Omron CP1L CPU UNIT - 03-2009, Operation Manual

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Auxiliary Area Allocations by Function Appendix C
Built-in Outputs
Pulse Outputs 0, 1
Name Description Read/Write Updated
High-speed Counter PV Contains the PV of the high-speed counter. Read-only • Cleared when power is turned ON.
• Cleared when operation starts.
• Updated each cycle during oversee-
ing process.
• Updated when PRV(881) instruction
is executed for the corresponding
counter.
High-speed
Counter Range
Comparison
Condition Met
Flags Range 1 These flags indicate whether the PV is within the
specified ranges when the high-speed counter is
being operated in range-comparison mode.
OFF: PV not in range
ON: PV in range Read-only • Cleared when power is turned ON.
• Cleared when operation starts.
• Cleared when range comparison
table is registered.
• Updated each cycle during oversee-
ing process.
• Updated when PRV(881) instruction
is executed to read range compari-
son results.
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
High-speed Counter Com-
parison In-progress Flag This flag indicates whether a comparison operation
is being executed for the high-speed counter.
OFF: Stopped.
ON: Being executed. Read-only • Cleared when power is turned ON.
• Cleared when operation starts.
• Updated when comparison operation
starts or stops.
High-speed Counter Over-
flow/Underflow Flag This flag indicates when an overflow or underflow
has occurred in the high-speed counter PV. (Used
with the linear mode counting range only.)
OFF: Normal
ON: Overflow or underflow Read-only • Cleared when power is turned ON.
• Cleared when operation starts.
• Cleared when the PV is changed.
• Updated when an overflow or under-
flow occurs.
High-speed Counter
Count Direction This flag indicates whether the high-speed counter
is currently being incremented or decremented. The
counter PV for the current cycle is compared with
the PLC in last cycle to determine the direction.
OFF: Decrementing
ON: Incrementing Read-only • Setting used for high-speed counter,
valid during counter operation.
High-speed Counter
Reset Bit When the reset method is set to Phase-Z
Software reset, the corresponding high-speed
counter's PV will be reset if the phase-Z signal is
received while this bit is ON.
When the reset method is set to a software reset,
the corresponding high-speed counter's PV will be
reset in the cycle when this bit goes ON. Read/Write • Cleared when power is turned ON.
High-speed Counter Gate
Bit When a counter's Gate Bit is ON, the counter's PV
will not be changed even if pulse inputs are received
for the counter.
When the bit is turned OFF again, counting will
restart and the high-speed counter's PV will be
updated.
When the reset method is set to Phase-Z
Software reset, the Gate Bit is disabled while the
corresponding Reset Bit is ON. Read/Write • Cleared when power is turned ON.
Item Pulse output
0
Pulse output
1
Pulse Output PV Leftmost 4 digits A277 A279
Rightmost 4 digits A276 A278
Pulse Output Accel/Decel Flag A280.00 A281.00
Pulse Output Overflow/Underflow Flag A280.01 A281.01
Pulse Output, Output Amount Set Flag A280.02 A281.02
Pulse Output, Output Completed Flag A280.03 A281.03
Pulse Output, Output In-progress Flag A280.04 A281.04
Pulse Output No-origin Flag A280.05 A281.05
Pulse Output At-origin Flag A280.06 A281.06
Pulse Output, Output Stopped Error Flag A280.07 A281.07
PWM Output, Output In-progress Flag A283.00 A283.08