Omron CP1L CPU UNIT - 03-2009, Operation Manual

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I/O Area and I/O Allocations Section 4-2
00 to 07 in CIO 0) and output bits CIO 101.00 to CIO 101.07 (i.e., bits 00 to 07
in CIO 1).
The upper bits (bits 12 to 15) not used in the input words cannot be used as
work bits. Only the bits not used in the output words can be used as work bits.
4-2-2 I/O Bits Allocated to Expansion I/O Units
There are Expansion I/O Units for expanding inputs, for expanding outputs,
and for expanding both input and outputs. I/O bits starting from bit 00 in the
next word after the word allocated to the previous Expansion Unit, Expansion
I/O Unit, or CPU Unit are automatically allocated. This word is indicated as
“CIO m” for input words and as “CIO n” for output words.
Unit Input bits Output bits
No. of
bits
No. of
words
Addresses No. of
bits
No. of
words
Addresses
Unit with 8 inputs CP1W-8ED
CPM1A-8ED 8 bits 1 word CIO m (bits 00 to 07) --- None None
Unit with
8 outputs Relays CP1W-8ER
CPM1A-8ER --- None None 8 bits 1 word CIO n (bits 00 to 07)
Sinking
transistors CP1W-8ET
CPM1A-8ET --- None None 8 bits 1 word CIO n (bits 00 to 07)
Sourcing
transistors CP1W-8ET1
CPM1A-8ET1 --- None None 8 bits 1 word CIO n (bits 00 to 07)
Unit with
16 out-
puts Relays CP1W-16ER
CPM1A-16ER --- None None 16 bits 2 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)
Sinking
transistors CP1W-16ET --- None None 16 bits 2 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)
Sourcing
transistors CP1W-16ET1 --- None None 16 bits 2 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)
Unit with
20 I/O Relays CP1W-20EDR1
CPM1A-20EDR1 12 bits 1 word CIO m (bits 00 to 11) 8 bits 1 word CIO n (bits 00 to 07)
Sinking
transistors CP1W-20EDT
CPM1A-20EDT 12 bits 1 word CIO m (bits 00 to 11) 8 bits 1 word CIO n (bits 00 to 07)
Sourcing
transistors CP1W-20EDT1
CPM1A-20EDT1 12 bits 1 word CIO m (bits 00 to 11) 8 bits 1 word CIO n (bits 00 to 07)
Unit
with 32
outputs Relays CP1W-32ER --- None None 32 bits 4 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)
CIO n+2 (bits 00 to 07)
CIO n+3 (bits 00 to 07)
Sinking
transistors CP1W-32ET --- None None 32 bits 4 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)
CIO n+2 (bits 00 to 07)
CIO n+3 (bits 00 to 07)
Sourcing
transistors CP1W-32ET1 --- None None 32 bits 4 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)
CIO n+2 (bits 00 to 07)
CIO n+3 (bits 00 to 07)
Unit with
40 I/O Relays CP1W-40EDR
CPM1A-40EDR 24 bits 2 words CIO m (bits 00 to 11)
CIO m+1 (bits 00 to 11)
16 bits 2 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)
Sinking
transistors CP1W-40EDT
CPM1A-40EDT 24 bits 2 words CIO m (bits 00 to 11)
CIO m+1 (bits 00 to 11)
16 bits 2 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)
Sourcing
transistors CP1W-40EDT1
CPM1A-40EDT1 24 bits 2 words CIO m (bits 00 to 11)
CIO m+1 (bits 00 to 11)
16 bits 2 words CIO n (bits 00 to 07)
CIO n+1 (bits 00 to 07)