Omron CP1L CPU UNIT - 03-2009, Operation Manual

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CPU Unit Operation Section 2-4
If high-speed response is required from input to output, execute IORF(097)
before and after the relevant instructions.
Note IORF(097) has a relatively long execution time which increases with the num-
ber of words being refreshed. Be sure to consider the affect of this time on the
overall cycle time. Refer to the
CP Series Programmable Controllers Program-
ming Manual for instruction execution times.
2-4-4 Initialization at Startup
The following initializing processes will be performed once each time the
power is turned ON.
• Confirm mounted Units and I/O allocations.
• Clear the non-holding areas of I/O memory according to the status of the
IOM Hold Bit. (See note 1.)
• Clear forced status according to the status of the Forced Status Hold Bit.
(See note 2.)
• Automatically transfer data from the Memory Cassette if one is mounted
and automatic transfer at startup is specified.
• Perform self-diagnosis (user memory check).
• Restore the user program. (See note 3.)
Note (1) The I/O memory is held or cleared according to the status of the IOM Host
Bit and the setting for IOM Hold Bit Status at Startup in the PLC Setup
(read only when power is turned ON).
Note When the mode is changed between PROGRAMMING mode and
RUN or MONITOR mode, I/O memory initialization is according to
the status of the IOM Hold Bit at that time.
(2) The forced status held or cleared according to the status of the Force Sta-
tus Hold Bit and the setting for Forced Status Hold Bit Status at Startup
in the PLC Setup (read only when power is turned ON).
IORF
St
E
IORF
2
5
Example
St : Starting word
E : End word
All the words from St to E, inclusive
are refreshed.
Here, the four words from CIO 2
to CIO 5 are refreshed.
Auxiliary bit
PLC Setup setting
IOM Hold Bit (A500.12)
Clear (OFF) Hold (ON)
IOM Hold Bit Status
at Startup Clear
(OFF) At power ON: Clear
At mode change: Clear At power ON: Clear
At mode change: Hold
Hold
(ON) At power ON: Hold
At mode change: Hold
Auxiliary bit
PLC Setup setting
Forced Status Hold Bit (A500.13)
Clear (OFF) Hold (ON)
Forced Status Hold
Bit Status at Startup Clear
(OFF) At power ON: Clear
At mode change: Clear At power ON: Clear
At mode change: Hold
Hold
(ON) At power ON: Hold
At mode change: Hold