Omron CP1L CPU UNIT - 03-2009, Operation Manual

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High-speed Counters Section 5-1
Restrictions
• There are no negative values in ring mode.
• If the max. ring count is set to 0 in the PLC Setup, the counter will operate
with a max. ring count of FFFFFFFF hex.
Reset Methods
Phase-Z Software
Reset The high-speed counter's PV is reset when the phase-Z signal (reset input)
goes from OFF to ON while the corresponding High-speed Counter Reset Bit
is ON.
The CPU Unit recognizes the ON status of the High-speed Counter Reset Bit
only at the beginning of the PLC cycle during the overseeing processes. Con-
sequently, when the Reset Bit is turned ON in the ladder program, the phase-
Z signal does not become effective until the next PLC cycle.
Software Reset The high-speed counter's PV is reset when the corresponding High-speed
Counter Reset Bit goes from OFF to ON.
The CPU Unit recognizes the OFF-to-ON transition of the High-speed
Counter Reset Bit only at the beginning of the PLC cycle during the oversee-
ing processes. Reset processing is performed at the same time. The OFF-to-
ON transition will not be recognized if the Reset Bit goes OFF again within the
same cycle.
Note The comparison operation can be set to stop or continue when a high-speed
counter is reset. This enables applications where the comparison operation
can be restarted from a counter PV of 0 when the counter is reset.
One cycle
Phase-Z
Reset Bit
PV not
reset
PV not
reset
PV
reset PV
reset
PV
reset PV
reset
One cycle
Reset Bit
PV not
reset PV
reset PV not
reset PV not
reset