Omron CP1L CPU UNIT - 03-2009, Operation Manual

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High-speed Counters Section 5-1
CPU Units with 14 I/O Points
Input terminal
block
Default setting High-speed counter operation settings Origin searches
Word Bit Single-phase
(increment pulse input)
Two-phase (differential
phases x4, up/down, or
pulse/direction)
Origin searches
enabled for pulse
outputs 0 and 1
CIO 0 00 Normal input 0 High-speed counter 0
(Increment) High-speed counter 0
(Phase A, Increment, or
Count input) ---
01 Normal input 1 High-speed counter 1
(Increment) High-speed counter 0
(Phase B, Decrement, or
Direction input) ---
02 Normal input 2 High-speed counter 2
(Increment) High-speed counter 1
(Phase A, Increment, or
Count input) Pulse output 0:
Origin proximity input
signal
03 Normal input 3 High-speed counter 3
(Increment) High-speed counter 1
(Phase B, Decrement, or
Direction input) Pulse output 1:
Origin proximity input
signal
04 Normal input 4 High-speed counter 0
(Phase Z or reset input) High-speed counter 0
(Phase Z or reset input) ---
05 Normal input 5 High-speed counter 1
(Phase Z or reset input) High-speed counter 1
(Phase Z or reset input) ---
06 Normal input 6 High-speed counter 2
(Phase Z or reset input) --- Pulse output 0:
Origin input signal
07 Normal input 7 High-speed counter 3
(Phase Z or reset input) --- Pulse output 1:
Origin input signal