UM10503
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User manual
Rev. 2.1 — 10 December 2015
1006 of 1441
NXP Semiconductors
UM10503
Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with
There is no “write-through” from Reload registers to Match registers. Before starting a
counter, software can write one value to the Match register used in the first cycle of the
counter and a different value to the corresponding Match Reload register used in the
second cycle.
31.3.21 SCT fractional match registers 0 to 5
Fractional Match registers are provided for up to the first six of the match registers. The
values programmed in these registers provide higher average resolution over time by
applying a dither pattern as described in
. This dither pattern results in
delaying recognition of a match for one counter clock for n (0 to 15) out of every 16
counter cycles. The value of n is programmed in these Fractional Match registers.
Fractional Match registers can be read at any time. Writing to a Fractional Match register
while the associated counter is running will not affect the register and will result in a bus
error.
Each Fractional Match register has a Fractional Match Reload register associated with it.
The contents of the reload registers are transferred into the Fractional Match registers at
the start of every new SCT counter cycle unless the NORELOAD bit for the appropriate
half-counter is set.
The reload registers may be written to at any time, regardless of whether or not the
counter is running.
There is no write-through from the Fractional Match Reload registers to the Fractional
Match registers. Before starting a counter, software can write one value to the Fractional
Match register that will be used in the first cycle or period of operation, and a different
value to the corresponding Fractional Match Reload register that will be used in the
second cycle or period.
An alternate addressing mode is available for all of the Fractional Match registers for DMA
access to halfword registers when UNIFY=0. See
Table 767. SCT match registers 0 to 15 (MATCH[0:15], address 0x4000 0100 (MATCH0) to
0x4000 4013C (MATCH15)) bit description (REGMODEn bit = 0)
Bit
Symbol
Description
Reset
value
15:0
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to
the L counter. When UNIFY = 1, read or write the lower 16 bits of
the 32-bit value to be compared to the unified counter.
0
31:16
MATCHn_H When UNIFY = 0, read or write the 16-bit value to be compared to
the H counter. When UNIFY = 1, read or write the upper 16 bits of
the 32-bit value to be compared to the unified counter.
0
