UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
424 of 1441
NXP Semiconductors
UM10503
Chapter 17: LPC43xx/LPC43Sxx System Control Unit (SCU)/ IO
17.4.6 ADC0 function select register
Remark:
See
for parts for which the ADC inputs are shared between the
ADC0 and ADC1.
For pins with digital and analog functions, this register selects the input channel of the
ADC0 over any of the possible digital functions. This option is not available for channel
ADC0_7.
In addition, each analog function is pinned out on a dedicated analog pin which is not
affected by this register.
The following pins are controlled by the ENAIO0 register:
3
SCL_EZI
Enable the input receiver for the SCL pin.
Always write a 1 to this bit when using the
I2C0.
0
R/W
0
Disabled
1
Enabled
6:4
-
Reserved
-
-
7
SCL_ZIF
Enable or disable input glitch filter for the
SCL pin. The filter time constant is
determined by bit SCL_EFP.
0
R/W
0
Enable input filter
1
Disable input filter
8
SDA_EFP
Select input glitch filter time constant for the
SDA pin.
0
R/W
0
50 ns glitch filter
1
3 ns glitch filter
9
-
Reserved. Always write a 0 to this bit.
0
R/W
10
SDA_EHD
Select I2C mode for the SDA pin.
0
R/W
0
Standard/Fast mode transmit
1
Fast-mode Plus transmit
11
SDA_EZI
Enable the input receiver for the SDA pin.
Always write a 1 to this bit when using the
I2C0.
0
R/W
0
Disabled
1
Enabled
14:12
-
Reserved
-
-
15
SDA_ZIF
Enable or disable input glitch filter for the
SDA pin. The filter time constant is
determined by bit SDA_EFP.
0
R/W
0
Enable input filter
1
Disable input filter
31:16
-
Reserved
-
-
Table 196. Pin configuration for open-drain I
2
C-bus pins register (SFSI2C0, address 0x4008
6C84) bit description
…continued
Bit
Symbol
Value
Description
Reset
value
Access
