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UM10503
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User manual
Rev. 2.1 — 10 December 2015
1333 of 1441
NXP Semiconductors
UM10503
Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1
47.6.5 A/D Status register
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the AD0/1DRn register for each A/D
channel n are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is
also found in ADSTAT.
47.7 Operation
47.7.1 Hardware-triggered conversion
If the BURST bit in the ADCR is 0 and the START field contains any value between 0x2
and 0x6, the A/D converter will start a conversion when a transition occurs on a selected
pin or Timer signal. The choices include the two ADCTRIG external input pins, an output
from the motocon PWM, and two combined timer outputs (see
).
The result of a hard-ware triggered conversion is stored in the individual channel data
registers DR0 to DR7. The global data register does not yield valid readings of a
hardware-triggered conversion.
47.7.2 Interrupts
An interrupt is requested to the NVIC when the ADINT bit in the ADSTAT register is 1. The
ADINT bit is one when any of the DONE bits of the A/D channels which are enabled for
interrupts (via the ADINTEN register) are one. Software can use the Interrupt Enable bit in
29:16 -
Reserved. Always 0.
0
30
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced
the result in the V_VREF bits in this register.This bit is cleared by
reading this register.
0
31
DONE
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
0
Table 1117. A/D Data registers (DR - addresses 0x400E 3010 (DR0) to 0x400E 302C (DR7)
(ADC0); 0x400E 4010 (DR0) to 0x400E 402C (DR7) (ADC1)) bit description
Bit
Symbol
Description
Reset
value
Table 1118. A/D Status register (STAT - address 0x400E 3030 (ADC0) and 0x400E 4030
(ADC1)) bit description
Bit
Symbol
Description
Reset
value
7:0
DONE
These bits mirror the DONE status flags that appear in the result
register for each A/D channel.
0
15:8
OVERUN
These bits mirror the OVERRRUN status flags that appear in the
result register for each A/D channel. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.
0
16
ADINT
This bit is the A/D interrupt flag. It is one when any of the individual
A/D channel Done flags is asserted and enabled to contribute to the
A/D interrupt via the ADINTEN register.
0
31:17 -
Reserved. Always 0.
0