NXP Semiconductors LPC43Sxx, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 457 of 1441
19.1 How to read this chapter
All GPIO register bit descriptions refer to up to 31 pins on each GPIO port. Depending on
the package type, not all pins are available, and the corresponding bits in the GPIO
registers are reserved (see
Table 241 ).
19.2 Basic configuration
The GPIO blocks share a common clock and reset connection and are configured as
follows:
•
See Table 242 for clocking and power control.
•
The GPIO is reset by a GPIO_RST (reset #28).
•
All GPIO pins are set to input by default. To read the signal on the GPIO input, enable
the input buffer in the SCU block for the corresponding pin (see
Table 192 to
Table 194 ).
•
For the pin interrupts, select up to 8 external interrupt pins from all GPIO port pins in
the SCU (see
Table 205 and Table 206 ). The pin interrupts must be enabled in the
NVIC (see Table 78 ).
•
The GPIO group interrupts must be enabled in the NVIC (see Table 78 ).
•
GPIO port registers can be accessed by the GPDMA as memory-to-memory transfer.
UM10503
Chapter 19: LPC43xx/LPC43Sxx GPIO
Rev. 2.1 — 10 December 2015 User manual
Table 241. GPIO pins for different pin packages
LBGA256 TFBGA180 TFBGA100 LQFP208 LQFP144 LQFP100
GPIO Port 0 GPIO0[15:0] GPIO0[15:0] GPIO0[4:0];
GPIO0[15:6] GPIO0[15:0] GPIO0[15:0] -
GPIO Port 1 GPIO1[15:0] GPIO1[15:0] GPIO1[15:0] GPIO1[15:0] GPIO1[15:0] -
GPIO Port 2 GPIO2[15:0] GPIO2[15:0] - GPIO2[15:0] GPIO2[15:0] -
GPIO Port 3 GPIO3[15:0] GPIO3[15:0] GPIO3[1:0];
GPIO3[5:3];
GPIO3[7] GPIO3[15:0] GPIO3[15:0] -
GPIO Port 4 GPIO4[15:0] GPIO4[15:0] - GPIO4[15:0] GPIO4[11] -
GPIO Port 5 GPIO5[26:0] GPIO5[26:0] GPIO5[11:0] GPIO5[25:0] GPIO5[16:0];
GPIO5[18] -
GPIO Port 6 GPIO6[30:0] GPIO6[26:25];
GPIO[30:28] - GPIO6[5:0];
GPIO6[30:20] - -
GPIO Port 7 GPIO7[25:0] GPIO7[4:0] - GPIO7[10:0];
GPIO7[21:17];
GPIO7[25:23] - -
Table 242. GPIO clocking and power control
Base clock Branch clock Operating
frequency
GPIO, GPIO pin interrupt, GPIO group0
interrupt, GPIO group1 interrupt BASE_M4_CLK CLK_M4_GPIO up to 204 MHz