UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
553 of 1441
NXP Semiconductors
UM10503
Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface
14
STOP_ABORT_CMD
Stop abort command. When open-ended or predefined data transfer
is in progress, and host issues stop or abort command to stop data
transfer, bit should be set so that command/data state-machines of
CIU can return correctly to idle state. This is also applicable for Boot
mode transfers. To Abort boot mode, this bit should be set along with
CMD[26] = disable_boot.
0
0
Disabled. Neither stop nor abort command to stop current data
transfer in progress. If abort is sent to function-number currently
selected or not in data-transfer mode, then bit should be set to 0.
1
Enabled. Stop or abort command intended to stop current data
transfer in progress.
15
SEND_INITIALIZATION
Send initialization. After power on, 80 clocks must be sent to card for
initialization before sending any commands to card. Bit should be set
while sending first command to card so that controller will initialize
clocks before sending command to card. This bit should not be set for
either of the boot modes (alternate or mandatory).
0
0
No. Do not send initialization sequence (80 clocks of 1) before
sending this command.
1
Send. Send initialization sequence before sending this command.
20:16
-
Reserved. Always write as 0.
0
21
UPDATE_CLOCK_
REGISTERS_ONLY
Update clock registers only. Following register values transferred into
card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card
clocks (change frequency, truncate off or on, and set low-frequency
mode); provided in order to change clock frequency or stop clock
without having to send command to cards. During normal command
sequence, when update_clock_registers_only = 0, following control
registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT,
CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new
command sequence to card(s). When bit is set, there are no
Command Done interrupts because no command is sent to
SD_MMC_CEATA cards.
0
0
Normal. Normal command sequence
1
No. Do not send commands, just update clock register value into card
clock domain
22
READ_CEATA_DEVICE
Read ceata device. Software should set this bit to indicate that
CE-ATA device is being accessed for read transfer. This bit is used to
disable read data time-out indication while performing CE-ATA read
transfers. Maximum value of I/O transmission delay can be no less
than 10 seconds.The SD/MMC interface should not indicate read data
time-out while waiting for data from CE-ATA device.
0
0
No read. Host is not performing read access (RW_REG or RW_BLK)
towards CE-ATA device.
1
Read. Host is performing read access (RW_REG or RW_BLK)
towards CE-ATA device.
Table 369. Command Register (CMD, address 0x4000 402C) bit description
Bit
Symbol
Value
Description
Reset
value
