UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
484 of 1441
NXP Semiconductors
UM10503
Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)
20.6.2 SGPIO multiplexer configuration registers
Each register controls one SGPIO multiplexer to select the following sources:
•
External clock source (when COUNT is not used)
•
External clock qualifier (static or controlled by a slice or external pin)
•
Input concatenation structure
SGPIO_MUX_CFG0 to SGPIO_MUX_CFG15 control slices A (register 0) to P (register
15).
To avoid oscillation, slices that can be a clock source for other slices cannot support
external slice clocks themselves (CLK_SOURCE_SLICE_MODE). These slices should
not feed a clock higher than SGPIO_CLOCK/2 to the other slices.
Fig 46. SGPIO local output pin multiplexer configuration
p_out_c fg
dout _doutm1
dout _doutm2
dout _doutm4
dout _doutm8
GP IO_RE G
c lk_out
p_oe_c fg
GP IO _OE RE G
dout_oem2
dout_oem4
dout_oem8
OUT_MUX _CFGx
doe
dout
5:4
3:0
dout_oem1
00
01
10
11
0000
00x x
01x x
10x x
0100
1000
11x x
p_oe_c fg
6
0
1
res erv ed
Table 276. SGPIO multiplexer configuration registers (SGPIO_MUX_CFG[0:15], addresses
0x4010 0040 (SGPIO_MUX_CFG0) to 0x4010 007C (SGPIO_MUX_CFG15)) bit
description
Bit
Symbol
Value Description
Reset
value
Access
0
EXT_CLK_ENABLE
Select clock signal.
0
R/W
0x0
Internal clock signal (slice)
0x1
External clock signal (pin)
