UM10503
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User manual
Rev. 2.1 — 10 December 2015
1084 of 1441
NXP Semiconductors
UM10503
Chapter 35: LPC43xx/LPC43Sxx Repetitive Interrupt Timer (RIT)
35.5.4 RI Counter register
35.6 RI timer operation
Following reset, the counter begins counting up from 0x0000 0000. Whenever the counter
value equals the value programmed into the COMPVAL register the interrupt flag will be
set. Any bit or combination of bits can be removed from this comparison (i.e. forced to
compare) by writing a ‘1’ to the corresponding bit(s) in the MASK register. If the enable_clr
bit is low (default state), a valid comparison ONLY causes the interrupt flag to be set. It
has no effect on the count sequence. Counting continues as usual. When the counter
reaches 0xFFFFFFFF it rolls-over to 0x000 00000 on the next clock and continues
counting. If the enable_clr bit is set to ‘1’ a valid comparison will also cause the counter to
be reset to zero. Counting will resume from there on the next clock edge.
Counting can be halted in software by writing a ‘0’ to the
RITEN
bit. Counting will also be
halted when the processor is halted for debugging provided the
RITENBR
bit is set. Both
the
RITEN
and
RITENBR
bits are set on reset.
The interrupt flag can be cleared in software by writing a ‘1’ to the
RITINT
bit.
Software can load the counter to any value at any time by writing to COUNTER.
The counter (COUNTER), COMPVAL register, MASK register and CTRL register can all
be read by software at any time.
Table 863. RI Counter register (COUNTER - address 0x400C 000C) bit description
Bit
Symbol
Description
Reset
value
31:0
RICOUNTER
32-bit up counter. Counts continuously unless RITEN bit in CTRL
register is cleared or debug mode is entered (if enabled by the
RITNEBR bit in CTRL). Can be loaded to any value in software.
0
