NXP Semiconductors LPC43Sxx, User Manual

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User manual Rev. 2.1 — 10 December 2015 120 of 1441
NXP Semiconductors
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Chapter 9: LPC43xx/LPC43Sxx Nested Vectored Interrupt Controller
9.7 Register description
The following table summarizes the registers in the NVIC. The Cortex-M4/M0 User
Guides provide a functional description of the NVIC registers.
29 45 0xB4 M0S_C_CAN0 -
30 46 0xB8 M0S_SPIFI_OR_ADCHS SPIFI OR ADCHS combined
interrupt
31 47 0xBC M0S_M0APP M0APP core
Table 80. Connection of interrupt sources to the Cortex-M0SUB subsystem NVIC
Interrupt
ID Exception
Number Vector
Offset Function Flag(s)
Table 81. Register overview: NVIC (base address 0xE000 E000)
Name Access Address
offset
Description Reset
value
ISER0 RW 0x100 Interrupt Set-Enable Register 0. This register allows enabling interrupts and
reading back the interrupt enables for specific peripheral functions. 0
ISER1 RW 0x104 Interrupt Set-Enable Register 1. This register allows enabling interrupts and
reading back the interrupt enables for specific peripheral functions. 0
ICER0 RW 0x180 Interrupt Clear-Enable Register 0. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions. 0
ICER1 RW 0x184 Interrupt Clear-Enable Register 1. This register allows disabling interrupts and
reading back the interrupt enables for specific peripheral functions. 0
ISPR0 RW 0x200 Interrupt Set-Pending Register 0. This register allows changing the interrupt
state to pending and reading back the interrupt pending state for specific
peripheral functions. 0
ISPR1 RW 0x204 Interrupt Set-Pending Register 1. This register allows changing the interrupt
state to pending and reading back the interrupt pending state for specific
peripheral functions. 0
ICPR0 RW 0x280 Interrupt Clear-Pending Register 0. This register allows changing the interrupt
state to not pending and reading back the interrupt pending state for specific
peripheral functions. 0
ICPR1 RW 0x284 Interrupt Clear-Pending Register 1. This register allows changing the interrupt
state to not pending and reading back the interrupt pending state for specific
peripheral functions. 0
IABR0 RO 0x300 Interrupt Active Bit Register 0. This register allows reading the current interrupt
active state for specific peripheral functions. 0
IABR1 RO 0x304 Interrupt Active Bit Register 1. This register allows reading the current interrupt
active state for specific peripheral functions. 0
IPR0 RW 0x400 Interrupt Priority Registers 0. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts. 0
IPR1 RW 0x404 Interrupt Priority Registers 1 This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts. 0
IPR2 RW 0x408 Interrupt Priority Registers 2. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts. 0
IPR3 RW 0x40C Interrupt Priority Registers 3. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts. 0
IPR4 RW 0x410 Interrupt Priority Registers 4. This register allows assigning a priority to each
interrupt. Each register contains the 3-bit priority fields for 4 interrupts. 0