UM10503
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User manual
Rev. 2.1 — 10 December 2015
163 of 1441
NXP Semiconductors
UM10503
Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC)
12.3.2 Power-down modes register PD0_SLEEP0_MODE
The PD0_SLEEP0_MODE register controls which of the three power-down modes,
Deep-sleep, Power-down, or Deep power-down is entered when an ARM WFE/WFI
instruction is issued and the SLEEPDEEP bit is set to 1 (SLEEPDEEP state).
Table 117. Hardware sleep event enable register (PD0_SLEEP0_HW_ENA - address
0x4004 2000) bit description
Bit
Symbol
Description
Reset
value
Access
0
ENA_EVENT0
Writing a 1 enables the Cortex-M4 core to put the part
into any of the Power-down modes Deep-sleep,
Power-down, or Deep power-down depending on the
value in the PD0_SLEEP0_MODE register.
1
R/W
1
ENA_EVENT1
Writing a 1 enables the Cortex-M0 core and the
Cortex-M0 subsystem core to put the part into any of
the Power-down modes Deep-sleep, Power-down, or
Deep power-down depending on the value in the
PD0_SLEEP0_MODE register.
0
R/W
31:2
-
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
-
-
Table 118. Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description
Bit
Symbol
Description
Reset
value
Access
31:0
PWR_STATE
Selects between Deep-sleep, Power-down, and
Deep power-down modes.
Only one of the following three values can be
programmed in this register:
0x0030 00AA = Deep-sleep mode
0x0030 FCBA = Power-down mode
0x0030 3CBA = Power-down mode with M0SUB
SRAM maintained
0x0030 FF7F = Deep power-down mode
0x0033
FF7F
R/W
