UM10503
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User manual
Rev. 2.1 — 10 December 2015
1214 of 1441
NXP Semiconductors
UM10503
Chapter 44: LPC43xx/LPC43Sxx I2S interface
44.7 Functional description
44.7.1 I2S transmit and receive interfaces
The I2S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio
information. Some details of the I2S implementation are:
•
When the transmit FIFO contains insufficient data the transmit channel will repeat
transmitting the last data until new data is available. This can occur when the
microcontroller or the DMA at some time are unable to provide new data fast enough.
Because of this delay in providing new data, there is a need to fill the gap, which is
accomplished by continuing to transmit the last sample. The data is not muted, as this
would produce a noticeable and undesirable sound effects.
•
When mute is true, the data value 0 is transmitted.
•
When mono is false, two successive data words are respectively left and right data.
•
The transmit channel and the receive channel FIFOs only handle 32-bit aligned
segments. Data chunks must be truncated or extended to a multiple of 32 bits. The
data word length is determined by the WORDWIDTH value in the configuration
register (see
). There is a separate WORDWIDTH value for the receive
channel and the transmit channel.
–
0: word is considered to contain four 8-bit data words.
–
1: word is considered to contain two 16-bit data words.
–
3: word is considered to contain one 32-bit data word.
When switching between different word widths or different modes, the I2S interface must
be reset via the reset bit in the control register in order to ensure correct synchronization.
It is advisable to set the stop bit also until sufficient data has been written in the transmit
FIFO. Note that when stopped, the data output is muted.
Data is read from the transmit FIFO after the falling edge of WS and will be transferred to
the transmit clock domain after the rising edge of WS. On the next falling edge of WS, the
left data will be loaded in the shift register and transmitted. On the following rising edge of
WS, the right data is loaded and transmitted.
The receive channel will start receiving data after a change of WS. When WS becomes
low it expects this data to be left data, when WS is high received data is expected to be
right data. Reception will stop when the bit counter has reached the limit set by the
WORDWIDTH value. On the next change of WS the received data will be stored in the
appropriate hold register. When complete data is available, it will be written into the
receive FIFO.
44.7.2 I2S operating modes
The clocking and WS usage of the I2S interface is fully configurable. In addition to master
and slave modes, which are independently configurable for the transmitter and the
receiver, several different clock sources are possible, including variations that share the
clock and/or WS between the transmitter and receiver. This last option allows using the
I2S interface with fewer pins, typically four.
provides an overview of the complete I2S interface. Specific operating modes
are explained in
and
