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UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
956 of 1441
NXP Semiconductors
UM10503
Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)
CAP0_L to CAP15_L
0x180 to
0x1A0
capture register of capture channel 0 to 15; low
counter 16-bit; REGMOD0_L to REGMODE15_L
= 1
0x0000 0000
CAP0_H to CAP15_H
0x1C0 to
0x1E0
capture register of capture channel 0 to 15; high
counter 16-bit; REGMOD0_H to REGMODE15_H
= 1
0x0000 0000
MATCHREL0 to
MATCHREL15
R/W
0x200 to
0x23C
SCT match reload value register 0 to 15;
REGMOD0 = 0 to REGMODE15 = 0
0x0000 0000
MATCHREL0_L to
MATCHREL15_L
R/W
0x200 to
0x23C
SCT match reload value register 0 to 15; low
counter 16-bit; REGMOD0_L = 0 to
REGMODE15_L = 0
0x0000 0000
MATCHREL0_H to
MATCHREL15_H
R/W
0x202 to
0x23E
SCT match reload value register 0 to 15; high
counter 16-bit; REGMOD0_H = 0 to
REGMODE15_H = 0
0x0000 0000
CAPCTRL0 to
CAPCTRL15
0x200 to
0x23C
SCT capture control register 0 to 15; REGMOD0
= 1 to REGMODE15 = 1
0x0000 0000
CAPCTRL0_L to
CAPCTRL15_L
0x200 to
0x23C
SCT capture control register 0 to 15; low counter
16-bit; REGMOD0_L = 1 to REGMODE15_L = 1
0x0000 0000
CAPCTRL0_H to
CAPCTRL15_H
0x202 to
0x23E
SCT capture control register 0 to 15; high counter
16-bit; REGMOD0 = 1 to REGMODE15 = 1
0x0000 0000
MATCHREL0_L to
MATCHREL15_L
R/W
0x280 to
0x2A0
SCT match reload value register 0 to 15; low
counter 16-bit; REGMOD0_L = 0 to
REGMODE15_L = 0
0x0000 0000
MATCHREL0_H to
MATCHREL15_H
R/W
0x2C0 to
0x2E0
SCT match reload value register 0 to 15; high
counter 16-bit; REGMOD0_H = 0 to
REGMODE15_H = 0
0x0000 0000
CAPCTRL0_L to
CAPCTRL15_L
0x280 to
0x2A0
).
SCT capture control register 0 to 15; low counter
16-bit; REGMOD0_L = 1 to REGMODE15_L = 1
0x0000 0000
CAPCTRL0_H to
CAPCTRL15_H
0x2C0 to
0x2E0
).
SCT capture control register 0 to 15; high counter
16-bit; REGMOD0 = 1 to REGMODE15 = 1
0x0000 0000
EVSTATEMSK0
R/W
0x300
SCT event state register 0
0x0000 0000
EVCTRL0
R/W
0x304
SCT event control register 0
0x0000 0000
EVSTATEMSK1
R/W
0x308
SCT event state register 1
0x0000 0000
EVCTRL1
R/W
0x30C
SCT event control register 1
0x0000 0000
EVSTATEMSK2
R/W
0x310
SCT event state register 2
0x0000 0000
EVCTRL2
R/W
0x314
SCT event control register 2
0x0000 0000
EVSTATEMSK3
R/W
0x318
SCT event state register 3
0x0000 0000
EVCTRL3
R/W
0x31C
SCT event control register 3
0x0000 0000
EVSTATEMSK4
R/W
0x320
SCT event state register 4
0x0000 0000
EVCTRL4
R/W
0x324
SCT event control register4
0x0000 0000
Table 716. Register overview: State Configurable Timer (base address 0x4000 0000)
…continued
Name
Access Address
offset
Description
Reset value
Reference