UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1040 of 1441
NXP Semiconductors
UM10503
Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM (MOTOCONPWM)
33.7.2 PWM Capture Control register
33.7.2.1 MCPWM Capture Control read address
The MCCAPCON register controls detection of events on the MCI0-2 inputs for all
MCPWM channels. Any of the three MCI inputs can be used to trigger a capture event on
any or all of the three channels. This address is read-only, but the underlying register can
be modified by writing to addresses CAPCON_SET and CAPCON_CLR.
4
DISUP0_CLR
Writing a one clears the corresponding bit in the CON register.
-
7:5
-
Writing a one clears the corresponding bit in the CON register.
-
8
RUN1_CLR
Writing a one clears the corresponding bit in the CON register.
-
9
CENTER1_CLR
Writing a one clears the corresponding bit in the CON register.
-
10
POLA1_CLR
Writing a one clears the corresponding bit in the CON register.
-
11
DTE1_CLR
Writing a one clears the corresponding bit in the CON register.
-
12
DISUP1_CLR
Writing a one clears the corresponding bit in the CON register.
-
15:1
3
-
Writing a one clears the corresponding bit in the CON register.
-
16
RUN2_CLR
Writing a one clears the corresponding bit in the CON register.
-
17
CENTER2_CLR
Writing a one clears the corresponding bit in the CON register.
-
18
POLA2_CLR
Writing a one clears the corresponding bit in the CON register.
-
19
DTE2_CLR
Writing a one clears the corresponding bit in the CON register.
-
20
DISUP2_CLR
Writing a one clears the corresponding bit in the CON register.
-
28:2
1
-
Writing a one clears the corresponding bit in the CON register.
-
29
INVBDC_CLR
Writing a one clears the corresponding bit in the CON register.
-
30
ACMOD_CLR
Writing a one clears the corresponding bit in the CON register.
-
31
DCMODE_CLR
Writing a one clears the corresponding bit in the CON register.
Table 804. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit description
Bit
Symbol
Description
Reset
value
Table 805. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit description
Bit
Symbol
Description
Reset
value
0
CAP0MCI0_RE
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.
0
1
CAP0MCI0_FE
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.
0
2
CAP0MCI1_RE
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.
0
3
CAP0MCI1_FE
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.
0
4
CAP0MCI2_RE
A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.
0
5
CAP0MCI2_FE
A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.
0
6
CAP1MCI0_RE
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.
0
7
CAP1MCI0_FE
A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.
0
8
CAP1MCI1_RE
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.
0
9
CAP1MCI1_FE
A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.
0
10
CAP1MCI2_RE
A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.
0
