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UM10503
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User manual
Rev. 2.1 — 10 December 2015
889 of 1441
NXP Semiconductors
UM10503
Chapter 28: LPC43xx/LPC43Sxx Ethernet
If software has enabled
Time stamp
ing through CSR, when a valid
Time stamp
value is not
available for the frame (for example, because the receive FIFO was full before the
Time
stamp
could be written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise
(that is, if
Time stamp
ing is not enabled), the RDES2 and RDES3 remain unchanged.
28.7.6.2.6
Receive descriptor acquisition
The Receive Engine always attempts to acquire an extra descriptor in anticipation of an
incoming frame. Descriptor acquisition is attempted if any of the following conditions is
satisfied:
•
The receive Start/Stop bit (DMA Operation Mode register
) has been set
immediately after being placed in the Run state.
•
The data buffer of current descriptor is full before the frame ends for the current
transfer.
•
The controller has completed frame reception, but the current Receive Descriptor is
not yet closed.
•
The receive process has been suspended because of a host-owned buffer
(RDES0[31] = 0) and a new frame is received.
•
A Receive poll demand has been issued.
28.7.6.2.7
Receive frame processing
The MAC transfers the received frames to the Host memory only when the frame passes
the address filter and frame size is greater than or equal to configurable threshold bytes
set for the Receive FIFO of MTL, or when the complete frame is written to the FIFO in
Store-and-Forward mode.
If the frame fails the address filtering, it is dropped in the MAC block itself (unless Receive
All bit 31 is set in the MAC Frame Filter register;
). Frames that are shorter than
64 bytes, because of collision or premature termination, can be purged from the MTL
Receive FIFO.
After 64 (configurable threshold) bytes have been received, the MTL block requests the
DMA block to begin transferring the frame data to the Receive Buffer pointed to by the
current descriptor. The DMA sets First Descriptor (RDES0[9]) after the DMA Host
Interface (AHB or MDC) becomes ready to receive a data transfer (if DMA is not fetching
transmit data from the host), to delimit the frame. The descriptors are released when the
Own (RDES[31]) bit is reset to 0, either as the Data buffer fills up or as the last segment of
the frame is transferred to the Receive buffer. If the frame is contained in a single
descriptor, both Last Descriptor (RDES[8]) and First Descriptor (RDES[9]) are set.
The DMA fetches the next descriptor, sets the Last Descriptor (RDES[8]) bit, and releases
the RDES0 status bits in the previous frame descriptor. Then the DMA sets Receive
Interrupt (Register 5[6]). The same process repeats unless the DMA encounters a
descriptor flagged as being owned by the host. If this occurs, the Receive Process sets
Receive Buffer Unavailable (DMA Status register
) and then enters the Suspend
state. The position in the receive list is retained.
28.7.6.2.8
Receive process suspended
If a new Receive frame arrives while the Receive Process is in Suspend state, the DMA
refetches the current descriptor in the Host memory. If the descriptor is now owned by the
DMA, the Receive Process re-enters the Run state and starts frame reception. If the