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UM10503
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User manual
Rev. 2.1 — 10 December 2015
3 of 1441
NXP Semiconductors
UM10503
LPC43xx/LPC43Sxx User manual
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Updated Figure 24 “IAP parameter passing”.
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Updated Figure 27 “Boot flow for encrypted images (flashless parts)”.
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Removed tge GPCLEAR_ENx bits from the register description. See Table 917 “Event
Monitor/Recorder Control Register (ERCONTRO, address 0x4004 6084) bit description”.
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Updated Table 1059 “CAN message interface message control registers (IF1_MCTRL, address
0x400E 2038 (C_CAN0) and 0x400A 4038 (C_CAN1)) bit description”: bit descriptions for bit 11 TXIE
is: 0 = The INTPND bit will be left unchanged after a successful transmission of a frame. 1 = INTPND
will be set after a successful transmission of a frame.
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In Table 118 “Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description”, the value of Deep power down mode is changed to 0x0033 FF7F.
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In Table 20 “OTP function allocation”, updated otp_ProgUSBID: otp_ProgUSBID will program prod_id
and vend_id in word 1 of bank 3: 3; word 1.
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Added a table note to Table 986 “SPI clocking and power control”:
BASE_SPI_CLK
0.5 * BASE_M4_CLK (if interrupt goes to M4 or M0APP).
BASE_SPI_CLK
0.5 * BASE_PERIPH_CLK (if interrupt goes to M0SUB).
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In Table 42 “ISP Go command”, updated the address description and example: This address must be
on a word boundary and it is not allowed to add the Thumb bit (bit 0) of the address. The example is
G 436208208 T<CR><LF>" branches to address 0x1A00 0250.
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Updated Table 24 “Boot image header description”: Reserved bits: 15: 8 instead of 15:14.
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Updated Table 74 “Boot image header description”: AES_CONTROL bits: 15:8. added a remark
before the table.
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Re-named Part ID register to CHIP ID register: Table 96 “Register overview: Configuration registers
(base address 0x4004 3000)” and Table 107 “Chip ID register (CHIPID, address 0x4004 3200) bit
description”. Added CHIP ID for Flash devices Rev A: CHIP ID is 0x7906 002B to Table 107 “Chip ID
register (CHIPID, address 0x4004 3200) bit description”.
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Added SBUSCFG register. See Table 463 “System bus interface configuration register (SBUSCFG -
address 0x4000 6090) bit description”. Added a remark in Section 25.6.10 “Burst Size register
(BURSTSIZE)”.
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Updated Figure 32 “AES endianness”.
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Added a bullet to Section 6.2 “Basic configuration”. If the application uses the IAP interface, it must
reserve the SRAM space used by IAP as outlined in Section 6.4.5.8 “RAM used by IAP command
handler”.
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Updated Section 6.4.5.8 “RAM used by IAP command handler”. Added text: 16 B of RAM from
0x10089FF0 to 0x10089FFF. Applications making use of IAP calls must reserve this RAM block.
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Updated Section 6.4.5.7 “RAM used by ISP”; removed command handler from the title and updated
text.
Revision history
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