NXP Semiconductors LPC43Sxx, User Manual

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User manual Rev. 2.1 — 10 December 2015 599 of 1441
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Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)
- - 0x00C -
0x01C Reserved. - - -
DYNAMICCONTROL R/W 0x020 Controls dynamic memory operation. 0x6 0x6 Table 418
DYNAMICREFRESH R/W 0x024 Configures dynamic memory refresh
operation. 0 0 Table 419
DYNAMICREADCONFIG R/W 0x028 Configures the dynamic memory read
strategy. 0 0 Table 420
- - 0x02C Reserved. - - -
DYNAMICRP R/W 0x030 Selects the precharge command period. 0xF 0xF Table 421
DYNAMICRAS R/W 0x034 Selects the active to precharge
command period. 0xF 0xF Table 422
DYNAMICSREX R/W 0x038 Selects the self-refresh exit time. 0xF 0xF Table 423
DYNAMICAPR R/W 0x03C Selects the last-data-out to active
command time. 0xF 0xF Table 424
DYNAMICDAL R/W 0x040 Selects the data-in to active command
time. 0xF 0xF Table 425
DYNAMICWR R/W 0x044 Selects the write recovery time. 0xF 0xF Table 426
DYNAMICRC R/W 0x048 Selects the active to active command
period. 0x1F 0x1F Table 427
DYNAMICRFC R/W 0x04C Selects the auto-refresh period. 0x1F 0x1F Table 428
DYNAMICXSR R/W 0x050 Selects the exit self-refresh to active
command time. 0x1F 0x1F Table 429
DYNAMICRRD R/W 0x054 Selects the active bank A to active bank
B latency. 0xF 0xF Table 430
DYNAMICMRD R/W 0x058 Selects the load mode register to active
command time. 0xF 0xF Table 431
- R/W 0x05C -
0x07C Reserved. - - -
STATICEXTENDEDWAIT R/W 0x080 Selects time for long static memory read
and write transfers. 0 0 Table 432
- R/W - Reserved. - - -
DYNAMICCONFIG0 R/W 0x100 Selects the configuration information for
dynamic memory chip select 0. 0 0 Table 433
DYNAMICRASCAS0 R/W 0x104 Selects the RAS and CAS latencies for
dynamic memory chip select 0. 0x303 0x303 Table 435
- 0x108 -
0x11C Reserved. - - -
DYNAMICCONFIG1 R/W 0x120 Selects the configuration information for
dynamic memory chip select 1. 0 0 Table 433
DYNAMICRASCAS1 R/W 0x124 Selects the RAS and CAS latencies for
dynamic memory chip select 1. 0x303 0x303 Table 435
- - 0x128 -
0x13C Reserved. - - -
Table 414. Register overview: External memory controller (base address 0x4000 5000)
…continued
Name Access Address
offset
Description Reset
value Reset
value
after
EMC
boot Reference