NXP Semiconductors LPC43Sxx, User Manual

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User manual Rev. 2.1 — 10 December 2015 1091 of 1441
NXP Semiconductors
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Chapter 37: LPC43xx/LPC43Sxx Real-Time Clock (RTC)
37.6.1 Interrupt Location Register
The Interrupt Location Register is a 2-bit register that specifies which blocks are
generating an interrupt. Writing a one to the appropriate bit clears the corresponding
interrupt. Writing a zero has no effect. This allows the programmer to read this register
and write back the same value to clear only the interrupt that is detected by the read.
37.6.2 Clock Control Register
The clock register is a 4-bit register that controls the operation of the clock divide circuit.
Bits 0, 1, and 4 in this register should be initialized when the RTC is first turned on.
[1] This register value is not changed by reset.
Table 878. Interrupt Location Register (ILR - address 0x4004 6000) bit description
Bit Symbol Description Reset
value
0 RTCCIF When one, the Counter Increment Interrupt block generated an
interrupt. Writing a one to this bit location clears the counter increment
interrupt. 0
1 RTCALF When one, the alarm registers generated an interrupt. Writing a one to
this bit location clears the alarm interrupt. 0
31:2 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
Table 879. Clock Control Register (CCR - address 0x4004 6008) bit description
Bit Symbol Value Description Reset
value
0 CLKEN Clock Enable. -
[1]
0 The time counters are disabled so that they may be initialized.
1 The time counters are enabled.
1 CTCRST CTC Reset. 0
0 No effect.
1 When one, the elements in the internal oscillator divider are
reset, and remain reset until this bit is changed to zero. This is
the divider that generates the 1 Hz clock from the 32.768 kHz
crystal. The state of the divider is not visible to software.
3:2 - Internal test mode controls. These bits must be 0 for normal
RTC operation. -
[1]
4 CCALEN Calibration counter enable. -
[1]
0 The calibration counter is enabled and counting, using the
1 Hz clock. When the calibration counter is equal to the value
of the CALIBRATION register, the counter resets and repeats
counting up to the value of the CALIBRATION register. See
Section 37.6.6.2 and Section 37.7.2 .
1 The calibration counter is disabled and reset to zero.
31:5 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA