UM10503
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User manual
Rev. 2.1 — 10 December 2015
602 of 1441
NXP Semiconductors
UM10503
Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)
[1]
The external memory cannot be accessed in low-power or disabled state. If a memory access is performed
an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled
state.
23.7.2 EMC Status register
The read-only Status register provides EMC status information.
Table 415. EMC Control register (CONTROL, address 0x4000 5000) bit description
Bit
Symbol
Value Description
Reset
value
0
E
EMC Enable. Indicates if the EMC is enabled or
disabled.Disabling the EMC reduces power consumption. When
the memory controller is disabled the memory is not refreshed.
The memory controller is enabled by setting the enable bit, or by
reset. This bit must only be modified when the EMC is in idle
state.
1
0
Disabled
1
Enabled. (POR and warm reset value).
1
M
Address mirror. Indicates normal or reset memory map. On POR,
CS1 is mirrored to both CS0 and DYCS0 memory areas.
Clearing the M bit enables CS0 and DYCS0 memory to be
accessed.
1
0
Normal. Normal memory map.
1
Reset. Reset memory map. Static memory CS1 is mirrored onto
CS0 and DYCS0 (POR reset value).
2
L
Low-power mode. Indicates normal, or low-power mode.
Entering low-power mode reduces memory controller power
consumption. Dynamic memory is refreshed as necessary. The
memory controller returns to normal functional mode by clearing
the low-power mode bit (L), or by POR.
This bit must only be modified when the EMC is in idle state.
0
0
Normal. Normal mode (warm reset value).
1
Low-power mode.
31:3
-
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
-
Table 416. EMC Status register (STATUS, address 0x4000 5004) bit description
Bit
Symbol
Value
Description
Reset
value
0
B
Busy indicator.
This bit is used to ensure that the memory controller enters
the low-power or disabled mode cleanly by determining if
the memory controller is busy or not:
1
0
Idle. EMC is idle (warm reset value).
1
Busy. EMC is busy performing memory transactions,
commands, auto-refresh cycles, or is in self-refresh mode
(POR reset value).
1
S
Write buffer status. This bit enables the EMC to enter
low-power mode or disabled mode cleanly:
0
0
Empty. Write buffers empty (POR reset value)
1
Data. Write buffers contain data.
