UM10503
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User manual
Rev. 2.1 — 10 December 2015
692 of 1441
NXP Semiconductors
UM10503
Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller
There is no data schedule mechanism for these transactions other than
micro-frame pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 ms) or else undefined
behavior may result.
25.8.1.9 Multiple Transaction Translators
The maximum number of embedded Transaction Translators that is currently supported is
one as indicated by the N_TT field in the HCSPARAMS – Host Control Structural
Parameters register.
25.8.2 Device operation
The co-existence of a device operational controller within the host controller has little
effect on EHCI compatibility for host operation except as noted in this section.
25.8.2.1 USBMODE register
Given that the dual-role controller is initialized in neither host nor device mode, the
USBMODE register must be programmed for host operation before the EHCI host
controller driver can begin EHCI host operations.
25.8.2.2 Non-Zero register fields
Some of the reserved fields and reserved addresses in the capability registers and
operational register are used in device mode.For read and write operations to these
register, note the following:
•
Always write zero to all EHCI reserved fields (some of which are device fields). This
is an EHCI requirement of the device controller driver.
•
Read operations by the host controller must properly mask EHCI reserved fields
(some of which are device fields) because fields that are used exclusively in device
mode are undefined in host mode.
25.8.2.3 SOF interrupt
This SOF Interrupt used for device mode is also used in host mode. In host mode, this
interrupt is raised every 125
s (high-speed mode). EHCI does not specify this interrupt
but it has been added for convenience and as a potential software time base. See
USBSTS (
) registers.
25.8.3 Deviations from EHCI
25.8.3.1 Discovery
25.8.3.1.1
Port reset
The port connect methods specified by EHCI require setting the port reset bit in the
PORTSC1 register for a duration of 10 ms. Due to the complexity required to support the
attachment of devices that are not high speed, there are counters already present in the
design that can count the 10 ms reset pulse to alleviate the burden on the software to
measure this duration. The basic connection is summarized as follows:
•
[Port Change Interrupt] Port connect change occurs to notify the host controller driver
that a device has attached.
