NXP Semiconductors LPC43Sxx, User Manual

Page: 1086 / 1441

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 1086 of 1441
NXP Semiconductors
UM10503
Chapter 36: LPC43xx/LPC43Sxx Alarm timer
36.4 Register description
36.4.1 Downcounter register
36.4.2 Preset value register
36.4.3 Interrupt clear enable register
Table 865. Register overview: Alarm timer (base address 0x4004 0000)
Name Access Address
offset Description Reset
value Reference
DOWNCOUNTER R/W 0x000 Downcounter register 0x000 Table 866
PRESET R/W 0x004 Preset value register 0x000 Table 867
- - 0x008 -
0xFD4 Reserved - -
CLR_EN W 0xFD8 Interrupt clear enable register 0x0 Table 868
SET_EN W 0xFDC Interrupt set enable register 0x0 Table 869
STATUS R 0xFE0 Status register 0x0 Table 870
ENABLE R 0xFE4 Enable register 0x0 Table 871
CLR_STAT W 0xFE8 Clear register 0x0 Table 872
SET_STAT W 0xFEC Set register 0x0 Table 873
Table 866. Downcounter register (DOWNCOUNTER - 0x4004 0000) bit description
Bit Symbol Description Reset value
15:0 CVAL When equal to zero an interrupt is raised.
When equal to zero PRESET is loaded and counting
continues.
0x0
31:16 - Reserved. -
Table 867. Preset value register (PRESET - 0x4004 0004) bit description
Bit Symbol Description Reset value
15:0 PRESETVAL Value loaded in DOWNCOUNTER when
DOWNCOUNTER equals zero. Example: PRESETVAL = 0
causes an interrupt every 1/1024 s, PRESETVAL = 1
causes an interrupt every 2/1024 s, etc. 0
31:16 - Reserved. -
Table 868. Interrupt clear enable register (CLR_EN - 0x4004 0FD8) bit description
Bit Symbol Description Reset value
0 CLR_EN Writing a 1 to this bit clears the interrupt enable bit in the
ENABLE register. 0
31:1 - Reserved. -