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UM10503
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User manual
Rev. 2.1 — 10 December 2015
878 of 1441
NXP Semiconductors
UM10503
Chapter 28: LPC43xx/LPC43Sxx Ethernet
in Ethernet. The controller can be programmed to interrupt the Host CPU for situations
such as Frame Transmit and Receive transfer completion, and other normal/error
conditions.
The DMA and the Host driver communicate through two data structures:
•
Control and Status registers (CSR). See
•
Descriptor lists and data buffers. See
.
The DMA transfers data frames received by the core to the Receive Buffer in the Host
memory, and Transmit data frames from the Transmit Buffer in the Host memory.
Descriptors that reside in the Host memory act as pointers to these buffers. There are two
descriptor lists; one for reception, and one for transmission. The base address of each list
is written into DMA Registers
and
. A descriptor list is forward linked
(either implicitly or explicitly). The last descriptor may point back to the first entry to create
a ring structure. Explicit chaining of descriptors is accomplished by setting the second
address chained in both Receive and Transmit descriptors (RDES1[24] and TDES1[24]).
The descriptor lists resides in the Host physical memory address space. Each descriptor
can point to a maximum of two buffers. This enables two buffers to be used, physically
addressed, rather than contiguous buffers in memory.
A data buffer resides in the Host physical memory space, and consists of an entire frame
or part of a frame, but cannot exceed a single frame. Buffers contain only data, buffer
status is maintained in the descriptor. Data chaining refers to frames that span multiple
data buffers. However, a single descriptor cannot span multiple frames. The DMA skips to
the next frame buffer when end-of-frame is detected. Data chaining can be enabled or
disabled.