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NXP Semiconductors LPC43Sxx, User Manual

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NXP Semiconductors LPC43Sxx User Manual Download Page 711

UM10503

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© NXP B.V. 2015. All rights reserved.

User manual

Rev. 2.1 — 10 December 2015 

711 of 1441

NXP Semiconductors

UM10503

Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller

25.10.8.3 Status phase

Similar to the data phase, the DCD must create a transfer descriptor (with byte length 
equal zero) and prime the endpoint for the status phase. The DCD must also perform the 
same checks of the ENDPTSETUPSTAT as described above in the data phase.

Remark: 

The MULT field in the dQH must be set to “00” for bulk, interrupt, and control 

endpoints.

Remark: 

Error handling of status phase packets is the same as bulk packets described 

previously.

25.10.8.4 Control endpoint bus response matrix

Shown in the following table is the device controller response to packets on a control 
endpoint according to the device controller state.

 

[1]

BS error = Force Bit Stuff Error

[2]

NYET/ACK – NYET unless the Transfer Descriptor has packets remaining according to the USB variable

length protocol then ACK.

[3]

SYSERR – System error should never occur when the latency FIFOs are correctly sized and the DCD is 
responsive.

25.10.9 Isochronous endpoint operational model

Isochronous endpoints are used for real-time scheduled delivery of data, and their 
operational model is significantly different from the host throttled Bulk, Interrupt, and 
Control data pipes. Real time delivery by the device controller is accomplished by the 
following:

•

Exactly MULT Packets per (micro) Frame are transmitted/received. Note: MULT is a 
two-bit field in the device Queue Head. The variable length packet protocol is not 
used on isochronous endpoints.

•

NAK responses are not used. Instead, zero length packets are sent in response to an 
IN request to an unprimed endpoint. For unprimed RX endpoints, the response to an 
OUT transaction is to ignore the packet within the device controller.

•

Prime requests always schedule the transfer described in the dTD for the next (micro) 
frame. If the ISO-dTD is still active after that frame, then the ISO-dTD will be held 
ready until executed or canceled by the DCD.

Table 515. Control endpoint bus response matrix

Token 
type

Endpoint state

Setup 
lockout

STALL

Not primed Primed

Underflow

Overflow

Setup

ACK

ACK

ACK

n/a

SYSERR

-

In

STALL

NAK

Transmit

BS error

n/a

n/a

Out

STALL

NAK

Receive and 
NYET/ACK

n/a

NAK

n/a

Ping

STALL

NAK

ACK

n/a

n/a

n/a

Invalid

Ignore

Ignore

Ignore

Ignore

Ignore

ignore

Summary of Contents for LPC43Sxx

Page 1: ...C4300 LPC4370 LPC4350 LPC4330 LPC4320 LPC4310 LPC4357 LPC4353 LPC4337 LPC4333 LPC4327 LPC4325 LPC4323 LPC4322 LPC4317 LPC4315 LPC4313 LPC4312 LPC43S50 LPC43S30 LPC43S20 LPC43S37 LPC43S57 LPC43S67 LPC4...

Page 2: ...e 5 LPC436x LPC43S6x block diagram parts with on chip flash dual core Updated Table 10 LPC43xx LPC43Sxx SRAM configuration to add LPC436x and LPC43S6x parts Updated Figure 10 Parts with on chip flash...

Page 3: ...42 ISP Go command updated the address description and example This address must be on a word boundary and it is not allowed to add the Thumb bit bit 0 of the address The example is G 436208208 T CR L...

Page 4: ...d by the boot code and the SPIFI API Use of IAP calls clarified IAP commands are not supported for flash less parts See Section 6 8 IAP commands For flashless parts only Unique part ID is stored in OT...

Page 5: ...USBINTR_H See Table 472 and Table 473 Bit 4 changed from Reserved to SEI in register USBSTS_D and USBSTS_H See Table 470 and Table 471 Bit 4 changed from Reserved to SEE in register USBINTR_D and USBI...

Page 6: ...ry map see Figure 7 for detailed addresses of all peripherals Section 36 7 1 Register read procedure updated for reading the RTC registers after wake up RTC_ALARM pin description corrected Table 871 R...

Page 7: ...ed Bits 9 0 changed to reserved Use bits 12 10 for disabling JTAG See Section 10 4 3 CREG5 control register Description of the RESET pin updated in Section 15 2 Pin description Use of EMC_CLK pins cla...

Page 8: ...er DEBNCE address 0x4000 4064 bit description updated Host clock is the SD_CLK clock Security features updates FIPS compliancy added ISP mode added to Figure 14 Boot process for parts without flash Re...

Page 9: ...sh filter with examples added Description of the I2C MASK register clarified Description of the I2C slave address updated UART1 TER register location and bit description corrected Polarity of the DMAC...

Page 10: ...T address 0x4001 1014 bit description Use of lower SPIFI memory clarified in Table SPIFI flash memory map Description of DAC DMA_ENA bit clarified in Table D A Control register CTRL address 0x400E 100...

Page 11: ...te values added Programming procedure for the SDRAM mode register added Clock ramp up procedures for core clock added Description of the event router updated 1 1 20120510 LPC43xx user manual Modificat...

Page 12: ...register map updated in Table 645 Changed maximum clock frequency for SWD and ETB access to 120 MHz Reduced and normal power modes removed AES encryption option added parts LPC43Sxx only SGPIO registe...

Page 13: ...essing and SIMD instructions A hardware floating point processor is integrated in the core The LPC43xx LPC43Sxx contain one or two ARM Cortex M0 processors to share computing tasks with the main ARM C...

Page 14: ...x LPC43S6x parts only Multiple SRAM blocks with separate bus access Two SRAM blocks can be powered down individually 64 kB ROM containing boot code and on chip software drivers General purpose One Tim...

Page 15: ...mode and with standard I O pins Two I2S interfaces each with DMA support and with one input and one output Digital peripherals External Memory Controller EMC supporting external SRAM ROM NOR flash an...

Page 16: ...n unit Crystal oscillator with an operating range of 1 MHz to 25 MHz 12 MHz Internal RC IRC oscillator trimmed to 1 5 flashless parts or 3 flash based parts accuracy over full temperature range and vo...

Page 17: ...le quad flat package 144 leads body 20 20 1 4 mm SOT486 1 LPC43S70FET256 LBGA256 Plastic low profile ball grid array package 256 balls body17 17 1 mm SOT740 2 LPC43S70FET100 TFBGA100 Plastic thin fine...

Page 18: ...e ball grid array package 256 balls body 17 17 1 mm SOT740 2 LPC4357JET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 17 1 mm SOT740 2 LPC4357JBD208 LQFP208 Plastic low prof...

Page 19: ...3S67JET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 17 1 mm SOT740 2 LPC43S67JBD208 LQFP208 Plastic low profile quad flat package 208 leads body 28 28 1 4 mm SOT459 1 LPC4...

Page 20: ...144 512 kB 512 kB 0 kB 104 kB no no yes no no yes no 8 J 83 LPC4322JET100 512 kB 512 kB 0 kB 104 kB no no yes no no no no 4 J 49 LPC4317JBD144 1 MB 512 kB 512 kB 136 kB no no no no no yes no 8 J 83 LP...

Page 21: ...IGH SPEED PHY 32 kB AHB SRAM 16 16 kB AHB SRAM SPIFI AES ENCRYPTION DECRYPTION 2 HS GPIO SPI SGPIO SCTimer PWM 64 kB ROM I2C0 I2S0 I2S1 C_CAN1 MOTOR CONTROL PWM 1 TIMER3 TIMER2 USART2 USART3 SSP1 RI T...

Page 22: ...ROM I2C0 I2S0 I2S1 C_CAN1 MOTOR CONTROL PWM TIMER3 TIMER2 USART2 USART3 SSP1 RI TIMER QEI GIMA BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE AHB MULTILAYER MATRIX LPC4370 128 kB LOCAL SRAM 72 kB LOCAL SR...

Page 23: ...I2S1 C_CAN1 MOTOR CONTROL PWM TIMER3 TIMER2 USART2 USART3 SSP1 RI TIMER QEI GIMA BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE AHB MULTILAYER MATRIX LPC43S70 128 kB LOCAL SRAM 72 kB LOCAL SRAM 10 bit ADC...

Page 24: ...T DEVICE EMC HIGH SPEED PHY SPIFI HS GPIO SCTimer PWM I2C0 I2S0 I2S1 C_CAN1 MOTOR CONTROL PWM 1 TIMER3 TIMER2 USART2 USART3 SSP1 RI TIMER QEI 1 GIMA BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE AHB MULT...

Page 25: ...ROL PWM TIMER3 TIMER2 USART2 USART3 SSP1 RI TIMER QEI GIMA BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE MAIN AHB MULTILAYER MATRIX AHB MULTILAYER MATRIX LPC436x 43S6x 10 bit ADC0 10 bit ADC1 C_CAN0 I2C1...

Page 26: ...A hardware floating point processor is integrated in the core The processor includes an NVIC with up to 53 interrupts The ARM Cortex M4 is implemented with a Memory Protection Unit supporting eight re...

Page 27: ...use the M0APPTXEVENT register Table 110 See Section 2 4 2 The ARM Cortex M0 subsystem core M0SUB is configured as follows See Table 5 for clocking and power control The ARM Cortex M0 subsystem core i...

Page 28: ...ARM Cortex M4 and to perform serial I O tasks The other ARM Cortex M0 core M0SUB if available is typically used to control the SGPIO and SPI peripherals This core is connected through a bridge to the...

Page 29: ...fferentiate messages for different CPU s for example the command in the command buffer could contain information for which CPU the command is intended The ARM Cortex M4 and ARM Cortex M0 trigger inter...

Page 30: ...age queues are located in the ARM Cortex M4 address space because the ARM Cortex M4 can be blocked from access to the ARM Cortex M0 hardware subsystem The M0 subsystem can be made more deterministic a...

Page 31: ...confirm that the write pointer will not be equal to or overtake the read pointer and will leave at least one free space On the other hand the receiving side shall promptly process and remove items fr...

Page 32: ...6 Command list Command Bit mask Description CMD_RD_ID 0xPPP0 TTTT read 32 bit WORD with argument ID 0xPPP from the task with ID 0xTTTT CMD_WR_ID 0xPPP1 TTTT WORD write 32 bit WORD with argument ID 0xP...

Page 33: ...alues in a reserved area in common SRAM memory An alternative approach is that the ARM Cortex M4 writes register per register However this requires more communication overhead than loading all data in...

Page 34: ...blocks are reserved 3 2 Basic configuration In the CREG block see Table 104 select the interface to access the 16 kB block of RAM located at address 0x2000 C000 This RAM memory block can be accessed...

Page 35: ...AHB SRAM AHB SRAM AHB SRAM ETB SRAM 2 0x1000 0000 0x1008 0000 0x1800 0000 0x2000 0000 0x2000 8000 0x2000 C000 LPC4370 128 kB 72 kB 16 2 kB 32 kB 16 kB 16 kB Figure 8 LPC4350 128 kB 72 kB 32 kB 16 kB 1...

Page 36: ...protected 3 3 5 Memory retention in the Power down modes In Deep sleep mode all SRAM content is retained At wake up the system can restart immediately In Power down mode only the top 8 kB of the SRAM...

Page 37: ...hest priority 0 lowest priority access permissions exporting memory attributes to the system MPU mismatches and permission violations invoke the programmable priority MemManage fault handler See the A...

Page 38: ...herals 3 0x2000 8000 16 kB AHB SRAM 16 kB AHB SRAM 0x2000 C000 16 kB AHB SRAM 16 kB AHB SRAM SGPIO SPI 0x4010 1000 0x4010 2000 0x4200 0000 reserved local SRAM external static memory banks 0x2000 0000...

Page 39: ...ls APB3 peripherals SGPIO SPI reserved 0x4010 1000 0x4010 2000 0x4200 0000 reserved external memories and ARM private bus APB2 peripherals 0x400C 1000 0x400C 2000 0x400C 3000 0x400C 4000 0x400C 6000 0...

Page 40: ...nductors UM10503 Chapter 3 LPC43xx LPC43Sxx Memory mapping 3 5 Memory map parts with on chip flash The memory map shown in Figure 10 and Figure 11 is global to both the Cortex M4 and the Cortex M0 pro...

Page 41: ...x4010 2000 0x4200 0000 reserved local SRAM external static memory banks 0x2000 0000 0x2001 0000 128 MB dynamic external memory DYCS0 256 MB dynamic external memory DYCS1 256 MB dynamic external memory...

Page 42: ...3000 0x400C 4000 0x400C 6000 0x400C 8000 0x400C 7000 0x400C 5000 0x400C 0000 RI timer USART2 USART3 timer2 timer3 SSP1 QEI APB1 peripherals 0x400A 1000 0x400A 2000 0x400A 3000 0x400A 4000 0x400A 5000...

Page 43: ...nstruction code I access Data D access and System S access The I and D bus access memory space is located below 0x2000 0000 the S bus accesses the memory space staring from 0x2000 0000 When instructio...

Page 44: ...less parts ARM CORTEX M4 TEST DEBUG INTERFACE ARM CORTEX M0 APPLICATION TEST DEBUG INTERFACE ARM CORTEX M0 SUBSYSTEM TEST DEBUG INTERFACE DMA ETHERNET USB1 USB0 LCD SD MMC EXTERNAL MEMORY CONTROLLER 3...

Page 45: ...M CORTEX M4 TEST DEBUG INTERFACE ARM CORTEX M0 APPLICATION TEST DEBUG INTERFACE ARM CORTEX M0 SUBSYSTEM TEST DEBUG INTERFACE DMA ETHERNET USB1 USB0 LCD SD MMC EXTERNAL MEMORY CONTROLLER 32 kB AHB SRAM...

Page 46: ...able are the boot source the USB vendor and product ID and the AES keys Unused fields can be used to store other data API support for programming the OTP in Boot ROM provided 4 3 General description T...

Page 47: ...purpose 0 no yes otp_ProgGP0 2 AES key 2 for data no no aes_ProgramKey2 User defined general purpose 1 no yes otp_ProgGP1 3 Word 0 Customer control data no yes otp_ProgBootSrc otp_ProgJTAGDis Word 0...

Page 48: ...programmable initial state 0 0x028 32 bit General purpose OTP memory 1 word 2 or AES key 2 word 2 2 3 User programmable initial state 0 0x02C 32 bit General purpose OTP memory 1 word 3 or AES key 2 w...

Page 49: ...1001 UART3 29 Reserved Do not write to this bit 30 Reserved Do not write to this bit 31 JTAG_DISABLE If this bit set JTAG cannot be enabled by software and remains disabled Table 16 OTP memory bank 3...

Page 50: ...evice Table 2 Ptr to Device Table 0 otp_Init Ptr to Function 2 Ptr to Function 0 Ptr to Function 1 Ptr to Function n OTP Driver 0x1040 0100 Device 0 ROM Driver Table 0x04 0x08 Ptr to OTP driver table...

Page 51: ...TP memory GP0 Use only if the device is not AES capable The data parameter consists of four 32 bit words one for each word in the memory bank The mask parameter contains a mask for each of the words w...

Page 52: ...therwise error code ERR_OTP_USB_ID_ENABLED is returned Parameter unsigned data unsigned mask Return unsigned see the general error codes 3 word 1 General purpose memory 2 word 0 otp_ProgGP2_1 0x24 Pro...

Page 53: ...on 11 n 5 2 Features The boot ROM memory includes the following features ROM memory size is 64 kB Supports booting from UART interfaces external static memory such as NOR flash SPI flash quad SPI flas...

Page 54: ...ns 0 0 0 0 Boot source is defined by the reset state of P1_1 P1_2 P2_9 and P2_8 pins See Table 22 USART0 0 0 0 1 Boot from device connected to USART0 using pins P2_0 and P2_1 For flash parts enter UAR...

Page 55: ...to be a valid image An example of a data set that would be interpreted as a valid image is a set in which the first eight words of flash bank A contain all zeros This implies that the data in the fir...

Page 56: ...determines the boot mode based on the OTP BOOT_SRC value or reset state of the pins P1_1 P1_2 P2_8 and P2_9 The boot ROM copies the image to internal SRAM at location 0x1000 0000 and jumps to that loc...

Page 57: ...or to copying to the internal SRAM If authentication fails the device is reset On non secure parts the image and header are not authenticated If the image is not preceded by a header then the image is...

Page 58: ...P1_2 P1_1 0 0 EMC 8b boot EMC 32b boot EMC 16b boot 1 10 enable JTAG no no valid Header yes yes no AES capable yes valid encrypted header and image hash authentic decrypt image to SRAM at 0x1000 0000...

Page 59: ...ialization vector iv 0 The user key is stored in the OTP see Table 13 Non encrypted images may omit the header 1 Can only be active if device is AES capable secure part Otherwise the image is consider...

Page 60: ...ustrated in Figure 17 configure the UART with the following settings Baudrate 115200 57600 38400 19200 or 9600 Data bits 8 Parity None Stop bits 1 Auto baud is active boot waits until 0x3F is received...

Page 61: ...are configured as pull down but not actively driven After reading the header the address bits are extended to be in line with the image size as defined by HASH_SIZE e g if HASH_SIZE is 100 kB then pin...

Page 62: ...w steps of the Quad SPI flash boot mode The execution of this mode occurs only if the boot mode is set accordingly see boot modes in Table 21 andTable 22 The boot code sets the SPIFI clock to 18 MHz a...

Page 63: ...with the SPIFI API Remark All QSPI devices have been tested at an operating voltage of 3 3 V Fig 20 SPIFI boot process Setup Pin Configuration P3_3 P3_8 Detect device device error activate Vendor_ID s...

Page 64: ...5 3 4 5 USB boot mode For booting from USB two USB interfaces are available USB0 supports high speed and full speed while USB1 supports only full speed This boot mode requires that a 12 MHz external c...

Page 65: ...with on chip flash booting from an external source Fig 21 USB boot process Setup clock USB_CLK 60MHz Setup VBUS pin P2_5 Boot source USB1 USB0 Setup clock USB_CLK 480MHz Enable HS PHY DFU enumerate re...

Page 66: ...he part resides in the end user board A LOW level on pin P2_7 after reset indicates hardware request to enter ISP mode ISP commands include preparing the on chip flash for erase and write operation re...

Page 67: ...6 4 5 8 RAM used by IAP command handler The ISP is configured as follows The ISP mode is entered when pin P2_7 is pulled LOW for parts with and without on chip flash On parts with on chip flash ISP c...

Page 68: ...Chapter 5 A LOW level after reset on pin P2_7 indicates an external hardware request to start the ISP command handler On parts with on chip flash the setting of the OTP bits and the boot pins determin...

Page 69: ...user program is found then the execution control is transferred to it If a valid user program is not found the boot process defaults to the ISP mode using USART0 and the auto baud routine is invoked P...

Page 70: ...rator of the serial port It also sends an ASCII string Synchronized CR LF to the host In response to this the host should send the same string Synchronized CR LF The auto baud routine looks at the rec...

Page 71: ...er ESC 0x1B This feature is not documented as a command under ISP Commands section Once the escape code is received the ISP command handler waits for a new command 6 4 5 6 Interrupts during IAP The on...

Page 72: ...3 8 0x1A00 6000 0x1A00 7FFF yes yes yes yes A 4 8 0x1A00 8000 0x1A00 9FFF yes yes yes yes A 5 8 0x1A00 A000 0x1A00 BFFF yes yes yes yes A 6 8 0x1A00 C000 0x1A00 DFFF yes yes yes yes A 7 8 0x1A00 E000...

Page 73: ...he following ISP commands and restrictions Read Memory command disabled Copy RAM to Flash command cannot write to Sector 0 Go command disabled Erase sectors command can erase any individual sector exc...

Page 74: ...upported or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED Table 33 Code Read Protection hardware software interaction CRP option User Code Valid P2_7 pin at r...

Page 75: ...lock Code yes yes Table 35 Set Baud Rate B Baud Rate stop bit yes yes Table 36 Echo A setting yes yes Table 37 Write to RAM W start address number of bytes yes yes Table 38 Read Memory R address numbe...

Page 76: ...ytes If the check sum matches the ISP command handler responds with OK CR LF to continue further transmission If the check sum does not match the ISP command handler responds with RESEND CR LF In resp...

Page 77: ...at location 0x1C00 0000 and from the internal flash Table 38 ISP Write to RAM command Command W Input Start Address RAM address where data bytes are to be written This address should be a word boundar...

Page 78: ...peration command Command P Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Flash bank Selects flash bank if the part supports more than on bank 0 fla...

Page 79: ...be written Should be 512 1024 4096 Return Code CMD_SUCCESS SRC_ADDR_ERROR Address not on word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERRO...

Page 80: ...ED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to execute a program residing in RAM or flash memory It may not be possible to return to the ISP command handler once this...

Page 81: ...ommand J Input None Return Code CMD_SUCCESS followed by part identification number in ASCII see Table 46 LPC43xx part identification numbers The command returns two words word0 followed by word1 Only...

Page 82: ...PC43S67JET256 8001C060 00000000 LPC43S67JET100 8001C060 00000000 LPC43S67JBD208 8001C060 00000000 Parts with on chip flash M4 M0 10 bit ADC LPC4357JET256 0xA001C830 0xXXXX XX00 LPC4357FET256 0xA001C83...

Page 83: ...LPC4313JBD144 0xA00BCB3F 0xXXXX XX44 LPC4313JET100 0xA00BCB3F 0xXXXX XX44 LPC4312JBD144 0xA00BCB3F 0xXXXX XX80 LPC4312JET100 0xA00BCB3F 0xXXXX XX80 Table 46 LPC43xx part identification numbers Device...

Page 84: ...d if CRP is enabled If CRP is included in the new flash image to be activated by this command ensure that the flash image content is executing as expected Otherwise the part may fail to boot after res...

Page 85: ...bank 0 flash bank A 1 flash bank B Return Code INVALID_FLASH_UNIT INVALID_SECTOR COMPARE_ERROR USER_CODE_CHECKSUM DST_ADDR_ERROR BUSY ERROR_SETTING_ACTIVE_PARTITION Description This command is only v...

Page 86: ...registers r0 and r1 The parameter table should be big enough to hold all the results in case the number of results are more than number of parameters Parameter passing is illustrated in Figure 24 The...

Page 87: ...t table to the IAP function unsigned int command_param 5 unsigned int status_result 5 or unsigned int command_param unsigned int status_result command_param unsigned int 0x status_result unsigned int...

Page 88: ...meter passing returning then it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces this risk The flash memor...

Page 89: ...write operations Stack usage 88 B Table 52 IAP Initialization command Command Init IAP Table 53 IAP Prepare sectors for write operation command Command Prepare sectors for write operation Input Comma...

Page 90: ...dary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY Result None Description This command is used to program the flash...

Page 91: ...is SECTOR_NOT_BLANK Result1 Contents of non blank word location Description This command is used to blank check a sector or multiple sectors of on chip flash memory To blank check a single sector use...

Page 92: ...Third 32 bit word of Device Identification Number Result3 Fourth 32 bit word of Device Identification Number Description This command is used to read the device identification number The serial numbe...

Page 93: ...his command ensure that the flash image content is executing as expected Otherwise the part may fail to boot after reset and for CRP level 3 external boot or ISP may not be accessible to update the fl...

Page 94: ...the host has been completely and successfully executed 0x0000 0001 INVALID_COMMAND Invalid command 0x0000 0002 SRC_ADDR_ERROR Source address is not on word boundary 0x0000 0003 DST_ADDR_ERROR Destinat...

Page 95: ...e g internal RAM can be executed during signature generation This can include interrupt services if the interrupt vector table is re mapped to memory other than the flash memory The code that initiate...

Page 96: ...he four registers FMSW0 FMSW1 FMSW2 and FMSW3 The generated flash signature can be used to verify the flash memory contents The generated signature can be compared with an expected signature and thus...

Page 97: ...alue 31 0 SW2 95 64 Word 2 of 128 bit signature bits 95 to 64 Table 71 FMSW3 register bit description FMSW3 address 0x4000 C038 flash A and 0x4000 D038 flash B Bit Symbol Description Reset Value 31 0...

Page 98: ...for the flash A safe estimation for the duration of the signature generation is Duration int 60 tcy 3 x FMSSTOP FMSSTART 1 When signature generation is triggered via software the duration is in AHB cl...

Page 99: ...sion 11 n 7 2 Features Secure booting from an encrypted image Cypher based Message Authentication Code CMAC authentication on the boot image Supports development mode for booting from a plain text ima...

Page 100: ...rypted header and image See Section 7 3 4 CMAC e Update the header with the calculated hash size f Encrypt header as before using CBC and an initialization vector of 0 2 On the LPC43Sxx program the en...

Page 101: ...ption encrypt data with CBC AES AES key User Key IV AES 1 User Key 1 512B 512B 512B 512B 0x3456 789A encrypt header with AES AES key User Key IV 0 calculate CMAC AES key User Key IV 0 define temporary...

Page 102: ...flow for encrypted images flashless parts check BOOT_SRC valid header yes no yes valid encrypted header and image hash authentic decrypt image to SRAM at 0x1000 0000 yes set program counter 0x1000 00...

Page 103: ...value in AES_CONTROL until the encrypted version does not contain the value 0x1A in the AES_ACTIVE field 1 Can only be active if device is AES capable else is considered an invalid image 2 16 extra b...

Page 104: ...3 The last block Mn should be padded to be a complete block and then Mn K1 Mn 4 Let c0 00 0 5 For i 1 n calculate ci AESK ci 1 Mi 6 Output T msbl cn The first message block is the header Since the CMA...

Page 105: ...ess timing parameters Parameter Description Value t_a Check boot selection pins 1 25 s t_b Initialize device 250 s 1 180 s 2 200 s 3 t_c Copy image to embedded SRAM If part is executing from external...

Page 106: ...AES API and passes the following tests diehard FIPS_140 1 NIST Data is processed in little endian mode This means that the first byte read from flash is integrated into the AES codeword as least sign...

Page 107: ...mand returns an error if the parts are not configured for encryption The AES encryption and decryption engine supports DMA for transferring data between memory and the AES engine The ROM based AES API...

Page 108: ...PI The AES is controlled through a set of simple API calls located in the LPC43Sxx ROM The API calls to the ROM are performed by executing functions which are pointed to by pointer within the ROM driv...

Page 109: ...d by the on chip random number generator Two APIs are provided to store keys in the OTP memory banks 1 and 2 Table 76 AES API calls Function Offset relative to the API entry point Description aes_Init...

Page 110: ...general error codes aes_Operate 0x20 Performs the AES encryption or decryption after the AES mode has been set using aes_Set_Mode and the appropriate keys and init vectors have been loaded Parameter1...

Page 111: ...peripheral control number is 13 Remark Selecting the AES input and output DMA request lines in the channel_id structure configures the DMAMUX register see Section 11 4 5 in the CREG block for AES aes...

Page 112: ...from OTP memory bank1 aes_LoadKey2 loads the non secure key from OTP memory bank2 aes_LoadKeyRNG loads a randomly generated key aes_LoadKeySW loads a key generated by the user code 3 If using CBC enco...

Page 113: ...f other Cipher Text frames This is useful when a random frame needs to be accessed 8 5 4 Use of AES keys The two hardware keys stored in OTP cannot be accessed by software and offer a high security le...

Page 114: ...ot in the physical otp memory Bits 31 0 at location 0x4004 5050 Bits 63 32 at location 0x4004 5054 Bits 95 64 at location 0x4004 5058 Bits 127 96 at location 0x4004 505C 3 Store this number in the RTC...

Page 115: ...C43Sxx each core is supports its own NVIC Each core can only access its own local NVIC registers 9 3 Features Nested Vectored Interrupt Controllers are integral parts of the ARM Cortex M4 and M0 proce...

Page 116: ...nterrupt numbers are used in some other contexts such as software interrupts In addition to the signals listed in Table 78 and Table 79 the NVIC handles the Non Maskable Interrupt NMI In order for NMI...

Page 117: ...nterrupt 28 44 0xB0 I2S0 29 45 0xB4 I2S1 30 46 0xB8 SPIFI 31 47 0xBC SGPIO 32 48 0xC0 PIN_INT0 GPIO pin interrupt 0 33 49 0xC4 PIN_INT1 GPIO pin interrupt 1 34 50 0xC8 PIN_INT2 GPIO pin interrupt 2 35...

Page 118: ...eserved 4 20 0x50 M0_FLASHEEPROMAT ORed flash bank A flash bank B EEPROM Atimer interrupts 5 21 0x54 M0_ETHERNET Ethernet interrupt 6 22 0x58 M0_SDIO SD MMC interrupt 7 23 0x5C M0_LCD 8 24 0x60 M0_USB...

Page 119: ...M4 core 2 18 0x48 M0S_DMA 3 19 0x4C Reserved 4 20 0x50 M0S_SGPIO_INPUT SGPIO input bit match 5 21 0x54 M0S_SGPIO_MATCH SGPIO pattern match 6 22 0x58 M0S_SGPIO_SHIFT SGPIO shift clock 7 23 0x5C M0S_SG...

Page 120: ...ng state for specific peripheral functions 0 ISPR1 RW 0x204 Interrupt Set Pending Register 1 This register allows changing the interrupt state to pending and reading back the interrupt pending state f...

Page 121: ...ty fields for 4 interrupts 0 IPR6 RW 0x418 Interrupt Priority Registers 6 This register allows assigning a priority to each interrupt Each register contains the 3 bit priority fields for 4 interrupts...

Page 122: ...7 In order to detect an event connected to any of the peripheral interrupts set the corresponding bit to HIGH in the HILO register the default setting of this register is LOW When using events 4 and 5...

Page 123: ...Deep power down modes Send a wake up signal to CCU1 and CCU2 for turning on wake up enabled branch clocks see Section 14 5 3 10 4 Event router inputs Fig 33 Event router block diagram WAKEUP3 2 WAKEU...

Page 124: ...ot active in Deep sleep Power down and Deep power down mode Use for wake up from Sleep mode 13 GIMA output 25 Output 2 of the combined timer ORed output of SCTimer PWM output 2 and the match channel 2...

Page 125: ...se wake up from any of the power down modes Table 85 Register overview Event router base address 0x4004 4000 Name Access Address offset Description Reset Value Reference HILO R W 0x000 Level configura...

Page 126: ...EDGE register is 1 1 Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0 Detect rising edge if bit 3 in the EDGE register is 1 4 ATIMER_L Level detect mode for alarm timer event 0...

Page 127: ...ster is 1 1 Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0 Detect rising edge if bit 9 in the EDGE register is 1 10 USB1_L Level detect mode for USB1 event 0 0 Detect LOW l...

Page 128: ...g edge if bit 15 in the EDGE register is 1 16 TIM14_L Level detect mode for combined timer output 14 event 0 0 Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0 Detect falling edg...

Page 129: ...0 Detect HIGH level 1 1 Detect rising edge Table 88 Edge configuration register EDGE address 0x4004 4004 bit description Bit Symbol Value Description Reset value 0 WAKEUP0_E Edge detect mode for WAKE...

Page 130: ...in the HILO register is 1 7 WWDT_E Edge level detect mode for WWDTD event The corresponding bit in the EDGE register must be 0 0 0 Level detect 1 Edge detect of the WWDT interrupt Detect falling edge...

Page 131: ...O register is 1 14 TIM6_E Edge level detect mode for combined timer output 6 event The corresponding bit in the EDGE register must be 0 0 0 Level detect 1 Edge detect of GIMA output 26 Detect falling...

Page 132: ...address 0x4004 4FD8 bit description Bit Symbol Description Reset value 0 WAKEUP0_CLREN Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register 1 WAKEUP1_CLREN Writing a 1 to this...

Page 133: ...rved Table 89 Clear event enable register CLR_EN address 0x4004 4FD8 bit description Bit Symbol Description Reset value Table 90 Event set enable register SET_EN address 0x4004 4FDC bit description Bi...

Page 134: ...ster 14 TIM6_SETEN Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register 15 QEI_SETEN Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register 16 TIM14_SETEN W...

Page 135: ...e WAKEUP2 event has been raised 1 3 WAKEUP3_ST A 1 in this bit shows that the WAKEUP3 event has been raised 1 4 ATIMER_ST A 1 in this bit shows that the ATIMER event has been raised 1 5 RTC_ST A 1 in...

Page 136: ...the event router interrupt when bit 0 1 in the STATUS register 0 6 BOD_EN A 1 in this bit shows that the BOD event has been enabled This event wakes up the chip and contributes to the event router in...

Page 137: ...vent has been enabled This event wakes up the chip and contributes to the event router interrupt when bit 0 1 in the STATUS register 0 31 22 Reserved Table 92 Event enable register ENABLE address 0x40...

Page 138: ...ing a 1 to this bit clears the STATUS event bit 20 in the STATUS register 21 DPDRESET_CLRST Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register 31 22 Reserved Table 93 Clear...

Page 139: ...er 13 TIM2_SETST Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register 14 TIM6_SETST Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register 15 QEI_SETST Writ...

Page 140: ...sters are reserved The following registers or register bits are implemented only on parts with on chip flash USB0FLADJ register USB1FLADJ register FALSHCFGA register FLASHCFGB register SAMPLECTRL bit...

Page 141: ...ed in the configuration register block ETB SRAM configuration BOD trip settings RTC Oscillator output DMA to peripheral muxing Ethernet mode Memory mapping Timer UART inputs USB PHY control RTC_ALARM...

Page 142: ...ping 0x1040 0000 0x1000 0000 0x1000 0000 Table 99 0x104 0x114 Reserved CREG5 R W 0x118 Chip configuration register 5 Controls JTAG access 0x4000 0260 Table 100 DMAMUX R W 0x11C DMA mux control Table 1...

Page 143: ...e after USB0 1 boot Reference Table 97 CREG0 register CREG0 address 0x4004 3004 bit description Bit Symbol Value Description Reset value Access 0 EN1KHZ Enable 1 kHz output 0 R W 0 1 kHz output disabl...

Page 144: ...t 13 12 SAMPLECTRL SAMPLE pin input output control 0 R W 0x0 Reserved 0x1 Sample output from the event monitor recorder 0x2 Output from the event router 0x3 Reserved 15 14 WAKEUP0CTRL WAKEUP0 pin inpu...

Page 145: ...re device Remark Disabling the JTAG can only be reversed by resetting the part through any available reset Table 98 CREG1 register CREG1 address 0x4004 3008 bit description Bit Symbol Value Descriptio...

Page 146: ...through a chip reset 0 R W 0 No effect 1 Disable JTAG debug Once JTAG is disabled JTAG access remains disabled until the chip is reset by any source 11 M4TAPSEL JTAG debug disable for M4 main processo...

Page 147: ...er1 match 0 0x1 UART1 transmit 0x2 I2S1 DMA request 1 0x3 SSP1 transmit 9 8 DMAMUXPER4 Select DMA to peripheral connection for DMA peripheral 4 0 R W 0x0 Timer1 match 1 0x1 UART1 receive 0x2 I2S1 DMA...

Page 148: ...connection for DMA peripheral 10 0 R W 0x0 SSP0 transmit 0x1 I2S0 DMA request 2 0x2 SCTimer PWM DMA request 0 0x3 Reserved 23 22 DMAMUXPER11 Selects DMA to peripheral connection for DMA peripheral 11...

Page 149: ...cess timing is set to a default value of 16 clocks Changing the FLASHCFG register value causes the flash accelerator to invalidate all of the holding latches resulting in new reads of flash informatio...

Page 150: ...bit description Bit Symbol Value Description Reset value 11 0 Reserved Do not change these bits from the reset value 0x3A 15 12 FLASHTIM Flash access time The value of this field plus 1 gives the num...

Page 151: ...ASE_M4_CLK clocks used for a flash access Warning Improper setting of this value may result in incorrect operation of the device All other values are allowed but may not be optimal for the supported c...

Page 152: ...timer outputs 1 SCTimer PWM outputs only SCTimer PWM outputs are used without timer match outputs 11 5 Reserved 12 I2S0_TX_SCK_IN_SEL I2S0_TX_SCK input select 0 R W 0 I2S Register I2S clock selected a...

Page 153: ...04 3130 bit description Bit Symbol Value Description Reset value Access 0 TXEVCLR Cortex M4 TXEV event 0 R W 0 Clear the TXEV event 1 No effect 31 1 Reserved Table 107 Chip ID register CHIPID address...

Page 154: ...justed Its initial programmed value is system dependent based on the accuracy of hardware USB clock This register should only be modified when the HCH bit in the USB STS register is one Changing value...

Page 155: ...eprogrammed by USB system software unless the default values are incorrect or the system is restoring the register while returning from a suspended state Remark The FLADJ register must be read only af...

Page 156: ...me length timing value The frame length is given in the number of high speed bit times in decimal format Each decimal value change to this register corresponds to 16 high speed bit times The SOF cycle...

Page 157: ...le WFI WFE instruction independently of whether the other cores are in active mode or in sleep mode System power down modes are initiated by a core but affect the entire system of cores peripherals an...

Page 158: ...ters Table 173 Table 172 Fig 34 Power mode transitions M0APP M0SUB active master PD0_SLEEP0_HW_ENA 0x2 M4 active M4 sleep M4 active master PD0_SLEEP0_HW_ENA 0x1 M0APP M0SUB reset M0APP M0SUB sleep M4...

Page 159: ...p sleep mode the CPU clock and peripheral clocks are shut down to save power logic states and SRAM memory are maintained All analog blocks and the BOD control circuit are powered down Remark Before en...

Page 160: ...sue a WFI or WFE instruction for the core or cores enabled in step 1 The part can wake up from Power down mode through a signal on any of the WAKEUP pins or a signal from the alarm timer or RTC Enable...

Page 161: ...Table 114 12 2 7 Memory retention in Power down modes Table 115 shows which parts of the SRAM memory are preserved in Sleep mode and the various power down modes In addition all FIFO memory contained...

Page 162: ...ng mode is set in the PD0_SLEEP0_MODE If all cores are enabled in this register the system will only enter a system power down mode once each cores have received a WFI WFE instruction For details see...

Page 163: ...nto any of the Power down modes Deep sleep Power down or Deep power down depending on the value in the PD0_SLEEP0_MODE register 1 R W 1 ENA_EVENT1 Writing a 1 enables the Cortex M0 core and the Cortex...

Page 164: ...down mode Description PD0_SLEEP0_MODE register bit settings Deep sleep CPU peripherals analog USB PHY in retention mode all SRAM supplies in active mode BOD in power down mode 0x0030 00AA Power down...

Page 165: ...gh operating frequencies To ramp up the clock frequency to an operating frequency above 110 MHz configure the core clock BASE_M4_CLK as described in Section 13 2 1 1 The recommended procedure to confi...

Page 166: ...ates in the mid frequency range 8 Wait 50 s 9 Set the PLL1 P divider to direct output mode DIRECT 1 The BASE_M4_CLK now operates in the high frequency range 13 2 1 2 Changing the BASE_M4_CLK after wak...

Page 167: ...1 for creating the core and peripheral clocks Oscillator control Clock generation and clock source multiplexing Integer dividers for clock output stages 13 4 General description The CGU generates mult...

Page 168: ...to the crystal oscillator are the XTAL pins The crystal oscillator creates one output to the clock source bus 3 PLLs PLL0USB PLL0AUDIO and PLL1 are controlled by the CGU Each PLL can select one input...

Page 169: ...480 MHz Base clock for USB0 2 BASE_PERIPH_CLK 204 MHz Base clock for Cortex M0SUB subsystem SPI and SGPIO 3 BASE_USB1_CLK 204 MHz Base clock for USB1 4 BASE_M4_CLK 204 MHz System base clock for ARM C...

Page 170: ...yes no no no no no IDIVD yes yes yes no no no no no IDIVE yes yes yes no no no no no Table 123 Clock sources for output stages Output stages d default clock source y yes clock source available n no c...

Page 171: ...stages d default clock source y yes clock source available n no clock source not available Clock sources BASE_SAFE_CLK BASE_USB0_CLK BASE_PERIPH_CLK BASE_USB1_CLK BASE_M4_CLK BASE_SPIFI_CLK BASE_SPI_C...

Page 172: ...mit clock ENET_RX_CLK I Ethernet PHY receive clock CLKOUT O Clock output pin CGU_OUT0 O CGU spare output 0 CGU_OUT1 O CGU spare output 1 Table 125 Register overview CGU base address 0x4005 0000 Name A...

Page 173: ...x0100 0000 0x0100 0000 Table 140 IDIVC_CTRL R W 0x050 Integer divider C control register 0x0100 0000 0x0900 0808 0x0900 0808 Table 140 IDIVD_CTRL R W 0x054 Integer divider D control register 0x0100 00...

Page 174: ...k BASE_ADCHS_CLK 0x0100 0000 0x0100 0000 0x0100 0000 Table 146 BASE_SDIO_CLK R W 0x090 Output stage 13 control register for base clock BASE_SDIO_CLK 0x0100 0000 0x0100 0000 0x0100 0000 Table 146 BASE_...

Page 175: ...y obtained by the following equation Note that the accuracy of this measurement can be affected by several factors 1 Quantization error is noticeable if the ratio between the two clocks is large e g 1...

Page 176: ...counter value 0 R 23 MEAS Measure frequency 0 R W 0 RCNT and FCNT disabled 1 Frequency counters started 28 24 CLK_SEL Clock source selection for the clock to be measured All other values are reserved...

Page 177: ...equency range 1 R W 0 Low Oscillator low frequency mode crystal or external clock source 1 to 20 MHz Between 15 MHz and 20 MHz the state of the HF bit is don t care 1 High Oscillator high frequency mo...

Page 178: ...ct input 0 R W 3 DIRECTO PLL0 direct output 0 R W 4 CLKEN PLL0 clock enable 0 R W 5 Reserved 6 FRM Free running mode 0 R W 7 Reserved 0 R W 8 Reserved Reads as zero Do not write one to this register 0...

Page 179: ...lowing code snippet SELR 0 bandwidth compute seli from msel unsigned anadeci_new unsigned msel unsigned tmp if msel 16384 return 1 if msel 8192 return 2 if msel 2048 return 4 if msel 501 return 8 if m...

Page 180: ...ed x 0x80 in switch nsel case 0 return 0xFFFFFFFF case 1 return 0x302 case 2 return 0x202 default for in nsel in PLL0_NSEL_MAX in x x x 2 x 3 x 4 1 7 x 1 0xFF return x The valid range for P psel is fr...

Page 181: ...LOCK PLL0 lock indicator 0 R 1 FR PLL0 free running indicator 0 R 31 2 Reserved Table 133 PLL0AUDIO control register PLL0AUDIO_CTRL address 0x4005 0030 bit description Bit Symbol Value Description Res...

Page 182: ...following code snippet For specific examples see Section 13 8 3 and Section 13 8 4 define PLL0_MSEL_MAX 1 15 multiplier compute mdec from msel 12 PLLFRACT_ REQ Fractional PLL word write request Set t...

Page 183: ...psel respectively The valid range for N nsel is from 1 to 2 8 This value is encoded into a 10 bit NDEC value The relationship can be expressed through the following code snippet define PLL0_NSEL_MAX 1...

Page 184: ...e fractional part of the PLLFRACT_CTRL register PLLFRACT 14 0 Consecutive M and M 1 values are then further encoded into appropriate MDEC values before being presented as input to the M divider 13 6 5...

Page 185: ...L1 input clock sent to post dividers default 2 Reserved Do not write one to this bit 0 R W 5 3 Reserved Do not write one to these bits 6 FBSEL PLL feedback select see Figure 40 PLL1 block diagram 0 R...

Page 186: ..._RX_CLK 0x03 ENET_TX_CLK 0x04 GP_CLKIN 0x05 Reserved 0x06 Crystal oscillator 0x07 PLL0USB 0x08 PLL0AUDIO 0x09 Reserved 0x0A Reserved 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserv...

Page 187: ...CLK 0x04 GP_CLKIN 0x06 Crystal oscillator 0x07 PLL0USB 0x08 PLL0AUDIO 0x09 PLL1 31 29 Reserved Table 139 IDIVA control register IDIVA_CTRL address 0x4005 0048 bit description continued Bit Symbol Valu...

Page 188: ...A 31 29 Reserved Table 140 IDIVB C D control registers IDIVB_CTRL address 0x4005 004C IDIVC_CTRL address 0x4005 0050 IDIVC_CTRL address 0x4005 0054 bit description Bit Symbol Value Description Reset v...

Page 189: ...on All other values are reserved 0x01 R W 0x00 32 kHz oscillator 0x01 IRC default 0x02 ENET_RX_CLK 0x03 ENET_TX_CLK 0x04 GP_CLKIN 0x06 Crystal oscillator 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 31 29 Rese...

Page 190: ...er down 0 R W 0 Enabled Output stage enabled default 1 Power down 10 1 Reserved 11 AUTOBLOCK Block clock automatically during frequency change 0 R W 0 Disabled Autoblocking disabled 1 Enabled Autobloc...

Page 191: ...K 0x04 GP_CLKIN 0x06 Crystal oscillator 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 144 BASE_PERIPH_CLK control register BASE_PERIPH_CLK addres...

Page 192: ...Crystal oscillator 0x07 PLL0USB 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 145 BASE_USB1_CLK control register BASE_USB1_CLK address 0x4005 00...

Page 193: ...K 0x03 ENET_TX_CLK 0x04 GP_CLKIN 0x06 Crystal oscillator 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 146 BASE_M4_CLK to BASE_UART3_CLK control...

Page 194: ...0x07 PLL0USB 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 147 BASE_OUT_CLK control register BASE_OUT_CLK addresses 0x4005 00AC bit description c...

Page 195: ...LK 0x04 GP_CLKIN 0x05 Reserved 0x06 Crystal oscillator 0x07 Reserved 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 148 BASE_AUDIO_CLK control reg...

Page 196: ...ing mode 13 7 3 Crystal oscillator The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU see Table 127 13 7 4 PLL0 PLL0USB and PLL0AUDIO The PLL blocks of the PLL0USB and PLL0A...

Page 197: ...ith handshake control Positive edge clocking Frequency limiter to avoid hang up of the PLL Lock detector Power down mode Free running mode Remark Both PLL0 blocks are functionally identical The PLL0 f...

Page 198: ...d This effectively prevents false lock indications and thus ensures a glitch free lock signal To avoid frequency hang up the PLL contains a frequency limiter This feature is built in to prevent the CC...

Page 199: ...fter the post divider 13 7 4 3 2 Mode 1a Normal operating mode without post divider and without pre divider In normal operating mode 1a the post divider and pre divider are bypassed The operating freq...

Page 200: ...set up the PLL0 follow these steps 1 Power down the PLL0 by setting bit 0 in the PLL0 control register PLL0USB_CTRL or PLL0AUDIO_CTRL to 1 This step is only needed if the PLL0 is currently enabled 2...

Page 201: ...z to 50 MHz input frequency The input from an external crystal is limited to 25 MHz 9 75 MHz to 320 MHz selectable output frequency with 50 duty cycle 156 MHz to 320 MHz Current Controlled Oscillator...

Page 202: ...d on to the input clock 13 7 6 3 Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks Only when this difference is smaller than the s...

Page 203: ...2 4 8 or 16 depending on the value of PSEL 1 0 automatically giving an output clock with a 50 duty cycle If a higher output frequency is needed the CCO clock can be sent directly to the output by set...

Page 204: ...vider is disabled and the CCO clock is sent directly to the output leading to the following frequency equation 5 Power down mode In this mode the internal current reference will be turned off the osci...

Page 205: ...of the BASE_APB1_CLK Using a crystal of 12 MHz as clock source a PLL1 multiplier of 10 and an integer divider of 4 provide the desired clock rate For this example program the CGU as follows 1 Enable t...

Page 206: ...gs for 480 MHz output clock Fclkin MHz PLL0USB_MDIV PLL0USB_NP_DIV Table 130 Table 131 1 0x073E 56C9 0x0030 2062 2 0x073E 2DAD 0x0030 2062 3 0x0B3E 34B1 0x0030 2062 4 0x0E3E 7777 0x0030 2062 5 0x0D32...

Page 207: ...0x133333 12 4 608 276 48 1 1 0x00001012 0x1147ae 512Fs 192 98 304 393 216 30 2 66 0x00002042 0x20c49b 96 49 152 491 52 11 514 5 0x00002005 0x147ae1 88 2 45 1584 451 584 2 1 5 0x00001005 0x1c3958 64 3...

Page 208: ...ider setting for 12 MHz with fractional divider bypassed Fs KHz Fout MHz Fcco MHz Error Hz NDEC MDEC PDEC PLL0AUDIO_ MDIV PLL0AUDIO_ NP_DIV Table 134 Table 135 128 Fs 192 24 576 491 52 0 63 13523 14 0...

Page 209: ...8 368 64 0 63 2665 24 0x00000a69 0x0003f018 22 05 11 2896 338 688 0 45 18810 24 0x0000497a 0x0002d018 16 8 192 409 6 0 61 18724 6 0x00004924 0x0003d006 12 6 144 307 2 0 5 30580 6 0x00007774 0x00005006...

Page 210: ...e EMC clock divider Table 164 together with bit 16 in the CREG6 register Table 105 Remark The CCU registers for a given branch clock are only read and write accessible when the branch clock is enabled...

Page 211: ...and I2S1 peripheral clock CLK_APB1_CAN1 Clock to the C_CAN1 register interface and C_CAN1 peripheral clock BASE_SPIFI_CLK CLK_SPIFI Clock for the SPIFI SCKI clock input BASE_M4_CLK CLK_M4_BUS M4 bus c...

Page 212: ...mer3 peripheral clock CLK_M4_SSP1 Clock to the SSP1 register interface CLK_M4_QEI Clock to the QEI register interface and QEI peripheral clock BASE_PERIPH_ CLK CLK_PERIPH_BUS Clock to the peripheral b...

Page 213: ...4 CLK_APB3_ADC1 status register 0x0000 0001 Table 166 CLK_APB3_CAN0_CFG R W 0x128 CLK_APB3_CAN0 configuration register 0x0000 0001 Table 163 CLK_APB3_CAN0_STAT R 0x12C CLK_APB3_CAN0 status register 0x...

Page 214: ...4_M4CORE_CFG R W 0x448 CLK_M4_M4CORE configuration register 0x0000 0001 Table 163 CLK_M4_M4CORE_STAT R 0x44C CLK_M4_M4CORE status register 0x0000 0001 Table 166 0x450 to 0x45C Reserved 0x460 to 0x464...

Page 215: ...configuration register 0x0000 0001 Table 163 CLK_M4_CREG_STAT R 0x53C CLK_M4_CREG status register 0x0000 0001 Table 166 0x540 to 0x5FC Reserved CLK_M4_RITIMER_CFG R W 0x600 CLK_M4_RITIMER configurati...

Page 216: ...1 Table 166 CLK_ADCHS_CFG R W 0xB00 CLK_ADCHS configuration register 0x0000 0001 Table 163 CLK_ADCHS_STAT R 0xB04 CLK_ADCHS status register 0x0000 0001 Table 166 Table 158 Register overview CCU1 base...

Page 217: ...of the branch clock 0x408 to 0x4FC Reserved CLK_APB0_USART0_CFG R W 0x500 CLK_APB0_UART0 configuration register 0x0000 0001 Table 165 CLK_APB0_USART0_STAT R 0x504 CLK_APB0_UART0 status register 0x000...

Page 218: ...R 5 4 Reserved 6 BASE_PERIPH_ CLK_IND Base clock indicator for BASE_PERIPH_CLK 0 All branch clocks switched off 1 At least one branch clock running 1 R 7 BASE_USB0_ CLK_IND Base clock indicator for B...

Page 219: ...ll active ensure that all transfers have completed before turning off the master clock in auto mode Otherwise data may be lost when the master clock is turned off and the master can t process a respon...

Page 220: ...echanism enable 0 R W 0 Auto is disabled 1 Auto is enabled 2 WAKEUP Wake up configure 0 R W 0 Wake up is disabled 1 Wake up is enabled 31 3 Reserved Table 164 CCU1 branch clock configuration register...

Page 221: ...V_CFG register for the divider status Table 165 CCU2 branch clock configuration register CLK_XXX_CFG addresses 0x4005 2100 0x4005 2200 0x4005 2800 bit description Bit Symbol Value Description Reset va...

Page 222: ...iption Reset value Access 0 RUN Run enable status 0 clock is disabled 1 clock is enabled 1 R 1 AUTO Auto AHB disable mechanism enable status 0 Auto is disabled 1 Auto is enabled 0 R 2 WAKEUP Wake up m...

Page 223: ...onfiguration 15 3 General description The RGU allows generation of independent reset signals for various blocks and peripherals on the LPC43xx Each reset signal is asserted by a reset generator with o...

Page 224: ...t Reset source Parts of the device reset when activated CORE_RST 0 external reset pin RESET BOD reset WWDT time out reset internal power failure exiting from Deep power down Entire chip except periphe...

Page 225: ...et TIMER2_RST 34 PERIPH_RST Timer2 reset TIMER3_RST 35 PERIPH_RST Timer3 reset RITIMER_RST 36 PERIPH_RST Repetitive Interrupt timer reset SCT_RST 37 PERIPH_RST State Configurable Timer reset MOTOCONPW...

Page 226: ...54 PERIPH_RST C_CAN1 reset CAN0_RST 55 PERIPH_RST C_CAN0 reset M0APP_RST 56 MASTER_RST ARM Cortex M0 co processor reset Remark Software must clear the M0 processor reset by writing to the RESET_CTRL1...

Page 227: ...ccess Address offset Description Reset value Reference RESET_CTRL0 W 0x100 Reset control register 0 see Table 172 RESET_CTRL1 W 0x104 Reset control register 1 see Table 173 RESET_STATUS0 R W 0x110 Res...

Page 228: ...W 0x444 Reset external status register 17 for USB0_RST 0x8 see Table 184 RESET_EXT_STAT18 R W 0x448 Reset external status register 18 for USB1_RST 0x8 see Table 184 RESET_EXT_STAT19 R W 0x44C Reset e...

Page 229: ...ternal status register 41 for ADC1_RST 0x4 see Table 183 RESET_EXT_STAT42 R W 0x4A8 Reset external status register 42 for DAC_RST 0x4 see Table 183 RESET_EXT_STAT43 0x4AC Reserved RESET_EXT_STAT44 R W...

Page 230: ...x4E0 Reset external status register 56 for M0APP_RST 0x8 see Table 184 RESET_EXT_STAT57 R W 0x4E4 Reset external status register 57 for SGPIO_RST 0x4 see Table 183 RESET_EXT_STAT58 R W 0x4E8 Reset ext...

Page 231: ...cleared to 0 after one clock cycle 0 W 19 DMA_RST Writing a one activates the reset This bit is automatically cleared to 0 after one clock cycle 0 W 20 SDIO_RST Writing a one activates the reset This...

Page 232: ...it is automatically cleared to 0 after one clock cycle 0 W 9 ADC1_RST Writing a one activates the reset This bit is automatically cleared to 0 after one clock cycle 0 W 10 DAC_RST Writing a one activa...

Page 233: ...t is automatically cleared to 0 after one clock cycle 0 W 26 SPI_RST Writing a one activates the reset This bit is automatically cleared to 0 after one clock cycle 0 W 27 Reserved 28 ADCHS_RST Writing...

Page 234: ...10 Reserved 11 Reset output activated by software write to RESET_CTRL register 01 R W 19 18 SCU_RST Status of the SCU_RST reset generator output 00 No reset activated 01 Reset output activated by inp...

Page 235: ...vated 01 Reset output activated by input to the reset generator 10 Reserved 11 Reset output activated by software write to RESET_CTRL register 01 R W 7 6 DMA_RST Status of the DMA_RST reset generator...

Page 236: ...vated 01 Reset output activated by input to the reset generator 10 Reserved 11 Reset output activated by software write to RESET_CTRL register 01 25 24 GPIO_RST Status of the GPIO_RST reset generator...

Page 237: ...vated by software write to RESET_CTRL register 01 R W 7 6 TIMER3_RST Status of the TIMER3_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator 10...

Page 238: ...TRL register 01 R W 23 22 Reserved 01 R W 25 24 UART0_RST Status of the UART0_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator 10 Reserved 11...

Page 239: ...activated by software write to RESET_CTRL register 01 R W 7 6 SSP1_RST Status of the SSP1_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator 10...

Page 240: ...L register 01 R W 21 20 SPI_RST Status of the SPI_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator 10 Reserved 11 Reset output activated by so...

Page 241: ...asserted 1 No reset 1 R 10 Reserved 1 11 Reserved 1 12 M0SUB_RST Current status of the M0SUB_RST 0 Reset asserted 1 No reset 0 R 13 M4_RST Current status of the M4_RST 0 Reset asserted 1 No reset 1 R...

Page 242: ...eset 1 R 28 GPIO_RST Current status of the GPIO_RST 0 Reset asserted 1 No reset 1 R 29 FLASHB_RST Current status of the FLASHB_RST 0 Reset asserted 1 No reset 1 R 30 Reserved 1 31 Reserved 1 Table 179...

Page 243: ...RST 0 Reset asserted 1 No reset 1 R 9 ADC1_RST Current status of the ADC1_RST 0 Reset asserted 1 No reset 1 R 10 DAC_RST Current status of the DAC_RST 0 Reset asserted 1 No reset 1 R 11 12 UART0_RST C...

Page 244: ...e SSP1_RST 0 Reset asserted 1 No reset 1 R 20 I2S_RST Current status of the I2S_RST 0 Reset asserted 1 No reset 1 R 21 SPIFI_RST Current status of the SPIFI_RST 0 Reset asserted 1 No reset 1 R 22 CAN1...

Page 245: ...aside from a software reset by writing to the RESET_CTRL register 15 4 4 2 Reset external status register 2 for MASTER_RST 15 4 4 3 Reset external status register 5 for CREG_RST Table 180 Reset exter...

Page 246: ...value of a flag at the start of execution Possible flag values are i 0xAA55 FF01 0xAA55 FF02 power on reset POR ii 0xAA55 FF01 external reset signal RESET iii 0xAA55 FF02 RGU generated core reset b A...

Page 247: ...LPC43Sxx Reset Generation Unit RGU a Check the state of the HILO EDGE registers and the RESET_E and RESET_ST bits in the EDGE and STATUS registers i HILO 0 EDGE 0 power on reset ii RESET_E 1 RESET_ST...

Page 248: ...e digital pins support an additional analog function selectable through the ENAIO registers in the SCU Remark Note that the pin name is not indicative of the GPIO port assigned to it 16 2 1 LPC4350 30...

Page 249: ...ived by the slave Corresponds to the signal WS in the I2S bus specification I O I2S1_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the...

Page 250: ...Master Out Slave in for SSP0 R Function reserved R Function reserved P1_3 P5 M2 J1 44 2 N PU I O GPIO0 10 General purpose digital input output pin O CTOUT_8 SCT output 8 Match output 0 of timer 2 I O...

Page 251: ...tput pin I CTIN_5 SCT input 5 Capture input 2 of timer 2 R Function reserved O EMC_WE LOW active Write Enable signal R Function reserved R Function reserved I O SGPIO14 General purpose digital input o...

Page 252: ...ternal memory data line 2 R Function reserved R Function reserved R Function reserved I O SD_DAT0 SD MMC data bus line 0 P1_10 R8 N6 H6 53 2 N PU I O GPIO1 3 General purpose digital input output pin I...

Page 253: ...put 0 of timer 0 R Function reserved I O SGPIO9 General purpose digital input output pin I SD_CD SD MMC card detect input P1_14 R11 K7 J8 61 2 N PU I O GPIO1 7 General purpose digital input output pin...

Page 254: ...O11 General purpose digital input output pin R Function reserved P1_18 N12 N10 J10 67 2 N PU I O GPIO0 13 General purpose digital input output pin I O U2_DIR RS 485 EIA 485 output enable direction con...

Page 255: ...s that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts I O GPIO5 0...

Page 256: ...ral purpose digital input output pin R Function reserved O T3_MAT0 Match output 0 of timer 3 O USB0_PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS mus...

Page 257: ...utput pin I O U0_DIR RS 485 EIA 485 output enable direction control for USART0 I O EMC_A10 External memory address line 10 O USB0_IND0 USB0 port indicator LED control output 0 I O GPIO5 6 General purp...

Page 258: ...timer 0 I O U3_BAUD Baud pin for USART3 I O EMC_A0 External memory address line 0 R Function reserved R Function reserved R Function reserved R Function reserved P2_10 G16 F14 E8 104 2 N PU I O GPIO0...

Page 259: ...nction reserved I O EMC_A4 External memory address line 4 R Function reserved R Function reserved R Function reserved I O U2_DIR RS 485 EIA 485 output enable direction control for USART2 P3_0 F13 D12...

Page 260: ...tter and read by the receiver Corresponds to the signal SD in the I2S bus specification I O I2S0_RX_SDA I2S Receive data It is driven by the transmitter and read by the receiver Corresponds to the sig...

Page 261: ...S transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I O I2S1_RX_WS Receive Word Select It is driven by the master and rec...

Page 262: ...ed R Function reserved O LCD_VD13 LCD data I O U3_UCLK Serial clock input output for USART3 in synchronous mode R Function reserved P4_1 A1 D3 3 5 N PU I O GPIO2 1 General purpose digital input output...

Page 263: ...l input output pin O CTOUT_2 SCT output 2 Match output 2 of timer 0 O LCD_VD1 LCD data R Function reserved R Function reserved O LCD_VD20 LCD data I O U3_DIR RS 485 EIA 485 output enable direction con...

Page 264: ...the slave Corresponds to the signal SCK in the I2S bus specification I O I2S0_TX_SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the I2S bus s...

Page 265: ...R Function reserved P5_1 P3 M1 39 2 N PU I O GPIO2 10 General purpose digital input output pin I MCI2 Motor control PWM channel 2 input I O EMC_D13 External memory data line 13 R Function reserved O...

Page 266: ...lear to Send input for UART 1 O T1_MAT0 Match output 0 of timer 1 R Function reserved R Function reserved P5_5 P10 N8 58 2 N PU I O GPIO2 14 General purpose digital input output pin O MCOA1 Motor cont...

Page 267: ...R15 P14 G5 74 2 N PU I O GPIO3 0 General purpose digital input output pin O EMC_DYCS1 SDRAM chip select 1 I O U0_UCLK Serial clock input output for USART0 in synchronous mode I O I2S0_RX_WS Receive W...

Page 268: ...R Function reserved I T2_CAP2 Capture input 2 of timer 2 R Function reserved R Function reserved P6_4 R16 M14 F6 80 2 N PU I O GPIO3 3 General purpose digital input output pin I CTIN_6 SCT input 6 Ca...

Page 269: ...purpose digital input output pin O USB0_IND1 USB0 port indicator LED control output 1 I O GPIO5 15 General purpose digital input output pin O T2_MAT0 Match output 0 of timer 2 R Function reserved R Fu...

Page 270: ...Function reserved O T2_MAT3 Match output 3 of timer 2 R Function reserved R Function reserved P6_12 G15 F13 103 2 N PU I O GPIO2 8 General purpose digital input output pin O CTOUT_7 SCT output 7 Matc...

Page 271: ...eceiver Corresponds to the signal SD in the I2S bus specification O LCD_VD18 LCD data O LCD_VD6 LCD data R Function reserved I U2_RXD Receiver input for USART2 I O SGPIO6 General purpose digital input...

Page 272: ...in O CTOUT_11 SCT output 1 Match output 3 of timer 2 R Function reserved O LCD_LP Line synchronization pulse STN Horizontal synchronization pulse TFT R Function reserved O TRACEDATA 2 Trace data bit 2...

Page 273: ...trol output 1 R Function reserved I MCI1 Motor control PWM channel 1 input I O SGPIO9 General purpose digital input output pin R Function reserved R Function reserved O T0_MAT1 Match output 1 of timer...

Page 274: ...n reserved I T0_CAP1 Capture input 1 of timer 0 P8_6 K3 J3 2 N PU I O GPIO4 6 General purpose digital input output pin I USB1_ULPI_NXT ULPI link NXT signal Data flow control signal from the PHY R Func...

Page 275: ...digital input output pin O MCOA2 Motor control PWM channel 2 output A R Function reserved R Function reserved I O I2S0_TX_WS Transmit Word Select It is driven by the master and received by the slave...

Page 276: ...urpose digital input output pin O ENET_TXD2 Ethernet transmit data 2 MII interface I O SGPIO4 General purpose digital input output pin I U3_RXD Receiver input for USART3 P9_5 M9 L7 69 2 N PU R Functio...

Page 277: ...2 N PU R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved O I2S1_RX_MCLK I2S1 receive master clock O CGU_OUT1 CGU spare clock output 1 R Function rese...

Page 278: ...l purpose digital input output pin R Function reserved R Function reserved R Function reserved PB_0 B15 D14 2 N PU R Function reserved O CTOUT_10 SCT output 10 Match output 3 of timer 3 O LCD_VD23 LCD...

Page 279: ...pose digital input output pin O CTOUT_8 SCT output 8 Match output 0 of timer 2 R Function reserved R Function reserved PB_4 B11 B10 2 N PU R Function reserved I O USB1_ULPI_D5 ULPI link bidirectional...

Page 280: ...nction reserved R Function reserved I O SD_CLK SD MMC card clock AI ADC1_1 ADC1 and ADC0 input channel 1 Configure the pin as USB1_ULPI_CLK input and use the ADC function select register in the SCU to...

Page 281: ...al data line 4 R Function reserved ENET_TX_EN Ethernet transmit enable RMII MII interface I O GPIO6 3 General purpose digital input output pin R Function reserved I T3_CAP1 Capture input 1 of timer 3...

Page 282: ...n R Function reserved O T3_MAT1 Match output 1 of timer 3 I SD_CD SD MMC card detect input PC_9 K2 2 N PU R Function reserved I USB1_ULPI_NXT ULPI link NXT signal Data flow control signal from the PHY...

Page 283: ...t data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I O SD_DAT5 SD MMC data bus line 5 PC_13 M1 2 N PU R Function reserved R Funct...

Page 284: ...pin O SD_POW SD MMC power monitor output R Function reserved I O SGPIO5 General purpose digital input output pin PD_2 R1 2 N PU R Function reserved O CTOUT_7 SCT output 7 Match output 3 of timer 1 I O...

Page 285: ...input output pin R Function reserved R Function reserved I O SGPIO9 General purpose digital input output pin PD_6 R6 2 N PU R Function reserved O CTOUT_10 SCT output 10 Match output 3 of timer 3 I O...

Page 286: ...put output pin R Function reserved R Function reserved I O SGPIO13 General purpose digital input output pin PD_10 P11 2 N PU R Function reserved I CTIN_1 SCT input 1 Capture input 1 of timer 0 Capture...

Page 287: ...purpose digital input output pin R Function reserved O CTOUT_13 SCT output 13 Match output 3 of timer 3 R Function reserved PD_14 R13 L11 2 N PU R Function reserved R Function reserved O EMC_DYCS2 SDR...

Page 288: ...ne 18 I O GPIO7 0 General purpose digital input output pin O CAN1_TD CAN1 transmitter output R Function reserved R Function reserved PE_1 N14 M12 2 N PU R Function reserved R Function reserved R Funct...

Page 289: ...reserved R Function reserved R Function reserved PE_5 N16 2 N PU R Function reserved O CTOUT_3 SCT output 3 Match output 3 of timer 0 O U1_RTS Request to Send output for UART 1 Can also be configured...

Page 290: ...pin R Function reserved R Function reserved R Function reserved PE_9 E16 2 N PU R Function reserved I CTIN_4 SCT input 4 Capture input 2 of timer 1 I U1_DCD Data Carrier Detect input for UART 1 I O E...

Page 291: ...IO7 12 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_13 G14 2 N PU R Function reserved O CTOUT_14 SCT output 14 Match output 2 of timer 3 I O...

Page 292: ...Function reserved R Function reserved R Function reserved R Function reserved O I2S1_TX_MCLK I2S1 transmit master clock PF_1 E11 2 N PU R Function reserved R Function reserved I O SSP0_SSEL Slave Sele...

Page 293: ...rved R Function reserved O I2S0_TX_MCLK I2S transmit master clock I O I2S0_RX_SCK I2S receive clock It is driven by the master and received by the slave Corresponds to the signal SCK in the I2S bus sp...

Page 294: ...CEDATA 2 Trace data bit 2 I O GPIO7 21 General purpose digital input output pin R Function reserved I O SGPIO6 General purpose digital input output pin I O I2S1_TX_WS Transmit Word Select It is driven...

Page 295: ...output for USART0 R Function reserved R Function reserved I O GPIO7 24 General purpose digital input output pin R Function reserved I SD_WP SD MMC card write protect input R Function reserved AI ADC0...

Page 296: ...TX_MCLK I2S1 transmit master clock CLK2 D14 P10 K6 99 4 O PU O EMC_CLK3 SDRAM clock 3 O CLKOUT Clock output pin R Function reserved R Function reserved I O SD_CLK SD MMC card clock O EMC_CLK23 SDRAM c...

Page 297: ...OTG this pin has an internal pull up resistor USB0_RREF H1 G1 F3 24 8 12 0 k accuracy 1 on board resistor to ground for current reference USB1 pins USB1_DP F12 D11 E9 89 9 I O USB1 bidirectional D lin...

Page 298: ...put channel 5 Shared between 10 bit ADC0 1 ADC0_6 ADC1_6 A5 A4 142 8 I IA I ADC input channel 6 Shared between 10 bit ADC0 1 ADC0_7 ADC1_7 C5 B5 136 8 I IA I ADC input channel 7 Shared between 10 bit...

Page 299: ...programming voltage VDDIO D7 E12 F7 F8 G10 H10 J6 J7 K7 L9 L10 N7 N13 H5 H10 K8 G10 F10 K5 5 36 41 71 77 107 111 141 12 I O power supply Tie the VDDREG and VDDIO pins to a common power supply to ensur...

Page 300: ...is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull up resistor through the pin s SFSP register 6 5 V tolerant transp...

Page 301: ...S bus specification P0_1 M2 G1 2 I PU I O GPIO0 1 General purpose digital input output pin I O SSP1_MOSI Master Out Slave in for SSP1 I ENET_COL Ethernet Collision detect MII interface I O SGPIO1 Gene...

Page 302: ...R Function reserved O SD_RST SD MMC reset signal for MMC4 4 card P1_4 T3 J2 2 I PU I O GPIO0 11 General purpose digital input output pin O CTOUT_9 SCT output 9 Match output 1 of timer 2 I O SGPIO11 G...

Page 303: ...ent unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC p...

Page 304: ...C_D4 External memory data line 4 R Function reserved R Function reserved R Function reserved I O SD_DAT2 SD MMC data bus line 2 P1_12 R9 K7 2 I PU I O GPIO1 5 General purpose digital input output pin...

Page 305: ...erface O T0_MAT1 Match output 1 of timer 0 R Function reserved R Function reserved R Function reserved P1_16 M7 H9 2 I PU I O GPIO0 3 General purpose digital input output pin I U2_RXD Receiver input f...

Page 306: ...the master and received by the slave Corresponds to the signal SCK in the I2S bus specification P1_20 M10 K10 2 I PU I O GPIO0 15 General purpose digital input output pin I O SSP1_SSEL Slave Select f...

Page 307: ...T3_CAP2 Capture input 2 of timer 3 R Function reserved P2_3 J12 D8 3 I PU I O SGPIO12 General purpose digital input output pin I O I2C1_SDA I2C1 data input output this pin does not use a specialized...

Page 308: ...ator LED control output 0 I O GPIO5 6 General purpose digital input output pin I CTIN_7 SCT input 7 I T3_CAP3 Capture input 3 of timer 3 R Function reserved P2_7 H14 C10 2 I PU I O GPIO0 7 General pur...

Page 309: ...r output for USART2 I O EMC_A1 External memory address line 1 R Function reserved R Function reserved R Function reserved R Function reserved P2_11 F16 A9 2 I PU I O GPIO1 11 General purpose digital i...

Page 310: ...nction reserved R Function reserved P3_1 G11 F7 2 I PU I O I2S0_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the I2S bus specificatio...

Page 311: ...us specification I O I2S1_RX_SDA I2S1 Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification O LCD_VD13 LCD data P3_5 C12 B7 2...

Page 312: ...O SPIFI_CS SPIFI serial flash chip select I O GPIO5 11 General purpose digital input output pin I O SSP0_SSEL Slave Select for SSP0 R Function reserved R Function reserved P4_0 D5 2 I PU I O GPIO2 0 G...

Page 313: ...DC0 input channel 0 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P4_4 B1 5 I PU I O GPIO2 4 General purpose digital input output pin O CTOUT_2...

Page 314: ...driven by the master and received by the slave Corresponds to the signal SCK in the I2S bus specification I O I2S0_TX_SCK Transmit Clock It is driven by the master and received by the slave Correspon...

Page 315: ...put 0 of timer 1 R Function reserved R Function reserved P5_1 P3 2 I PU I O GPIO2 10 General purpose digital input output pin I MCI2 Motor control PWM channel 2 input I O EMC_D13 External memory data...

Page 316: ...line 8 R Function reserved I U1_CTS Clear to Send input for UART 1 O T1_MAT0 Match output 0 of timer 1 R Function reserved R Function reserved P5_5 P10 2 I PU I O GPIO2 14 General purpose digital inpu...

Page 317: ...ion reserved R Function reserved P6_1 R15 G5 2 I PU I O GPIO3 0 General purpose digital input output pin O EMC_DYCS1 SDRAM chip select 1 I O U0_UCLK Serial clock input output for USART0 in synchronous...

Page 318: ...EMC_CAS LOW active SDRAM Column Address Strobe R Function reserved R Function reserved R Function reserved R Function reserved P6_5 P16 F9 2 I PU I O GPIO3 4 General purpose digital input output pin...

Page 319: ...l input output pin O USB0_IND0 USB0 port indicator LED control output 0 I O GPIO5 16 General purpose digital input output pin O T2_MAT1 Match output 1 of timer 2 R Function reserved R Function reserve...

Page 320: ...ed R Function reserved R Function reserved R Function reserved P7_0 B16 2 I PU I O GPIO3 8 General purpose digital input output pin O CTOUT_14 SCT output 14 Match output 2 of timer 3 R Function reserv...

Page 321: ...7 LCD data O LCD_VD5 LCD data R Function reserved R Function reserved R Function reserved P7_4 C8 5 I PU I O GPIO3 12 General purpose digital input output pin O CTOUT_13 SCT output 13 Match output 1 o...

Page 322: ...output pin AI ADC1_6 ADC1 input channel 6 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P8_0 E5 3 13 I PU I O GPIO4 0 General purpose digital i...

Page 323: ...D2 ULPI link bidirectional data line 2 R Function reserved O LCD_VD12 LCD data O LCD_VD19 LCD data R Function reserved R Function reserved O T0_MAT3 Match output 3 of timer 0 P8_4 J2 2 I PU I O GPIO4...

Page 324: ...terrupt transfers to the PHY R Function reserved O LCD_VD4 LCD data O LCD_PWR LCD panel power enable R Function reserved R Function reserved I T0_CAP3 Capture input 3 of timer 0 P8_8 L1 2 I PU R Funct...

Page 325: ...by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I ENET_RXD3 Ethernet receive data 3 MII interface I O SGPIO2 General purpose digital input output...

Page 326: ...dicating over current condition this signal monitors over current on the USB1 bus external circuitry required to detect over current condition R Function reserved R Function reserved I ENET_COL Ethern...

Page 327: ...r Interface PHA input R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved PA_4 G13 2 I PU R Function reserved O CTOUT_9 SCT output 9...

Page 328: ...nction reserved I O GPIO5 22 General purpose digital input output pin O CTOUT_7 SCT output 7 Match output 3 of timer 1 R Function reserved R Function reserved PB_3 A13 2 I PU R Function reserved I O U...

Page 329: ...channel 6 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PC_0 D4 5 13 I PU R Function reserved I USB1_ULPI_CLK ULPI link CLK signal 60 MHz clock...

Page 330: ...PIO6 2 General purpose digital input output pin R Function reserved R Function reserved O SD_VOLT1 SD MMC bus voltage select output 1 AI ADC1_0 ADC1 input channel 0 Configure the pin as GPIO input and...

Page 331: ...General purpose digital input output pin R Function reserved O T3_MAT0 Match output 0 of timer 3 I O SD_DAT3 SD MMC data bus line 3 PC_8 N4 2 I PU R Function reserved I O USB1_ULPI_D0 ULPI link bidire...

Page 332: ...ata bus line 4 PC_12 L6 2 I PU R Function reserved R Function reserved O U1_DTR Data Terminal Ready output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 R F...

Page 333: ...devices R Function reserved I O GPIO6 14 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO4 General purpose digital input output pin PD_1 P1 2 I PU R Function...

Page 334: ...I O GPIO6 18 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO8 General purpose digital input output pin PD_5 P6 2 I PU R Function reserved O CTOUT_9 SCT outpu...

Page 335: ...GPIO6 22 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO12 General purpose digital input output pin PD_9 T11 2 I PU R Function reserved O CTOUT_13 SCT outpu...

Page 336: ...ved I O GPIO6 26 General purpose digital input output pin R Function reserved O CTOUT_10 SCT output 10 Match output 2 of timer 2 R Function reserved PD_13 T14 2 I PU R Function reserved I CTIN_0 SCT i...

Page 337: ...R Function reserved I O GPIO6 30 General purpose digital input output pin O SD_VOLT2 SD MMC bus voltage select output 2 O CTOUT_12 SCT output 12 Match output 0 of timer 3 R Function reserved PE_0 P14...

Page 338: ...ral purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_4 K13 2 I PU R Function reserved I NMI External interrupt input to NMI R Function reserved I O EMC_A...

Page 339: ...6 External memory data line 26 I O GPIO7 7 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_8 F14 2 I PU R Function reserved O CTOUT_4 SCT output...

Page 340: ...ART 1 I O EMC_D30 External memory data line 30 I O GPIO7 11 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_12 D15 2 I PU R Function reserved O...

Page 341: ...ecialized I2C pad O EMC_CKEOUT3 SDRAM clock enable 3 I O GPIO7 15 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PF_0 D12 2 O PU I O SSP0_SCK Seri...

Page 342: ...Function reserved PF_4 D10 H4 2 O PU I O SSP1_SCK Serial clock for SSP1 I GP_CLKIN General purpose clock input to the CGU O TRACECLK Trace clock R Function reserved R Function reserved R Function rese...

Page 343: ..._MOSI Master Out Slave in for SSP1 O TRACEDATA 2 Trace data bit 2 I O GPIO7 21 General purpose digital input output pin R Function reserved I O SGPIO6 General purpose digital input output pin I O I2S1...

Page 344: ...13 I PU R Function reserved O U0_TXD Transmitter output for USART0 R Function reserved R Function reserved I O GPIO7 24 General purpose digital input output pin R Function reserved I SD_WP SD MMC card...

Page 345: ...2S1_TX_MCLK I2S1 transmit master clock CLK2 D14 K6 4 O PU O EMC_CLK3 SDRAM clock 3 O CLKOUT Clock output pin R Function reserved R Function reserved I O SD_CLK SD MMC card clock O EMC_CLK23 SDRAM cloc...

Page 346: ...y 1 on board resistor to ground for current reference USB1 pins USB1_DP F12 E9 9 I O USB1 bidirectional D line USB1_DM G12 E10 9 I O USB1 bidirectional D line I2C bus pins I2C0_SCL L15 D6 10 I F I O I...

Page 347: ...cuit RTCX2 B8 B5 8 O Output from the RTC 32 kHz ultra low power oscillator circuit Crystal oscillator pins XTAL1 D1 B1 8 I Input to the oscillator circuit and internal clock generator circuits XTAL2 E...

Page 348: ...glitch filter 5 V tolerant if VDD IO present if VDD IO not present do not exceed 3 3 V providing digital I O functions with TTL levels and hysteresis high drive strength 5 5 V tolerant pad with 15 ns...

Page 349: ...tionality When power is switched off this pin connected to the I2C bus is floating and does not disturb the I2C lines 12 5 V tolerant pad with 20 ns glitch filter provides digital I O functions with o...

Page 350: ...nal WS in the I2S bus specification I O I2S1_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the I2S bus specification P0_1 M2 G1 50 34...

Page 351: ...erved I O SSP0_MOSI Master Out Slave in for SSP0 R Function reserved I O EMC_D14 External memory data line 14 P1_3 P5 J1 61 44 2 N PU I O GPIO0 10 General purpose digital input output pin O CTOUT_8 SC...

Page 352: ...igital input output pin I CTIN_5 SCT input 5 Capture input 2 of timer 2 R Function reserved O EMC_WE LOW active Write Enable signal R Function reserved O EMC_BLS0 LOW active Byte Lane select signal 0...

Page 353: ...ut 3 of timer 2 I O EMC_D2 External memory data line 2 R Function reserved R Function reserved R Function reserved I O SD_DAT0 SD MMC data bus line 0 P1_10 R8 H6 75 53 2 N PU I O GPIO1 3 General purpo...

Page 354: ...I T0_CAP0 Capture input 0 of timer 0 R Function reserved I O SGPIO9 General purpose digital input output pin I SD_CD SD MMC card detect input P1_14 R11 J8 85 61 2 N PU I O GPIO1 7 General purpose digi...

Page 355: ...1 transmitter output I O SGPIO11 General purpose digital input output pin R Function reserved P1_18 N12 J10 95 67 2 N PU I O GPIO0 13 General purpose digital input output pin I O U2_DIR RS 485 EIA 485...

Page 356: ...e pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB_PPWR...

Page 357: ...ure input 1 of timer 2 I O GPIO5 3 General purpose digital input output pin R Function reserved O T3_MAT0 Match output 0 of timer 3 O USB0_PPWR VBUS drive signal towards external charge pump or power...

Page 358: ...purpose digital input output pin I CTIN_7 SCT input 7 I T3_CAP3 Capture input 3 of timer 3 O EMC_BLS1 LOW active Byte Lane select signal 1 P2_7 H14 C10 138 96 2 N PU I O GPIO0 7 General purpose digit...

Page 359: ...t for USART2 I O EMC_A1 External memory address line 1 R Function reserved R Function reserved R Function reserved R Function reserved P2_11 F16 A9 148 105 2 N PU I O GPIO1 11 General purpose digital...

Page 360: ...ster clock I O I2S0_TX_SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the I2S bus specification O I2S0_TX_MCLK I2S transmit master clock I O S...

Page 361: ...O SPI_SCK Serial clock for SPI I O SSP0_SCK Serial clock for SSP0 O SPIFI_SCK Serial clock for SPIFI O CGU_OUT1 CGU spare clock output 1 R Function reserved O I2S0_TX_MCLK I2S transmit master clock I...

Page 362: ...O SPIFI_MISO Input 1 in SPIFI quad mode SPIFI output IO1 R Function reserved I O SSP0_MISO Master In Slave Out for SSP0 R Function reserved R Function reserved P3_7 C11 D7 176 123 2 N PU R Function re...

Page 363: ...erface AI ADC0_1 ADC0 and ADC1 input channel 1 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P4_2 D3 12 8 2 N PU I O GPIO2 2 General purpose dig...

Page 364: ...n select register in the SCU to select the DAC P4_5 D2 15 10 2 N PU I O GPIO2 5 General purpose digital input output pin O CTOUT_5 SCT output 5 Match output 3 of timer 3 O LCD_FP Frame pulse STN Verti...

Page 365: ...input 5 Capture input 2 of timer 2 O LCD_VD9 LCD data R Function reserved I O GPIO5 12 General purpose digital input output pin O LCD_VD22 LCD data O CAN1_TD CAN1 transmitter output I O SGPIO13 Genera...

Page 366: ...configured to be an RS 485 EIA 485 output enable signal for UART 1 I T1_CAP1 Capture input 1 of timer 1 R Function reserved R Function reserved P5_2 R4 63 46 2 N PU I O GPIO2 11 General purpose digita...

Page 367: ...9 R Function reserved I U1_DCD Data Carrier Detect input for UART 1 O T1_MAT1 Match output 1 of timer 1 R Function reserved R Function reserved P5_6 T13 89 63 2 N PU I O GPIO2 15 General purpose digit...

Page 368: ...K Serial clock input output for USART0 in synchronous mode I O I2S0_RX_WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the I2S bus specifica...

Page 369: ...apture input 1 of timer 3 O U0_TXD Transmitter output for USART0 O EMC_CAS LOW active SDRAM Column Address Strobe R Function reserved R Function reserved R Function reserved R Function reserved P6_5 P...

Page 370: ...output pin O USB0_IND0 USB0 port indicator LED control output 0 I O GPIO5 16 General purpose digital input output pin O T2_MAT1 Match output 1 of timer 2 R Function reserved R Function reserved P6_9 J...

Page 371: ...ction reserved R Function reserved R Function reserved P7_0 B16 158 110 2 N PU I O GPIO3 8 General purpose digital input output pin O CTOUT_14 SCT output 14 Match output 2 of timer 3 R Function reserv...

Page 372: ...VD5 LCD data R Function reserved R Function reserved R Function reserved P7_4 C8 189 132 5 N PU I O GPIO3 12 General purpose digital input output pin O CTOUT_13 SCT output 13 Match output 3 of timer 3...

Page 373: ...pin AI ADC1_6 ADC1 and ADC0 input channel 6 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P8_0 E5 2 3 N PU I O GPIO4 0 General purpose digital...

Page 374: ...link bidirectional data line 2 R Function reserved O LCD_VD12 LCD data O LCD_VD19 LCD data R Function reserved R Function reserved O T0_MAT3 Match output 3 of timer 0 P8_4 J2 39 2 N PU I O GPIO4 4 Ge...

Page 375: ...transfers to the PHY R Function reserved O LCD_VD4 LCD data O LCD_PWR LCD panel power enable R Function reserved R Function reserved I T0_CAP3 Capture input 3 of timer 0 P8_8 L1 49 2 N PU R Function...

Page 376: ...transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I ENET_RXD3 Ethernet receive data 3 MII interface I O SGPIO2 General purpose digital input output pin I O...

Page 377: ...gital input output pin O MCOB1 Motor control PWM channel 1 output B I USB1_PWR_FAULT USB1 Port power fault signal indicating over current condition this signal monitors over current on the USB1 bus ex...

Page 378: ...ace PHA input R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved PA_4 G13 151 2 N PU R Function reserved O CTOUT_9 SCT output 9 Mat...

Page 379: ...eserved I O GPIO5 22 General purpose digital input output pin O CTOUT_7 SCT output 7 Match output 3 of timer 1 R Function reserved R Function reserved PB_3 A13 178 2 N PU R Function reserved I O USB1_...

Page 380: ...6 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PC_0 D4 7 5 N PU R Function reserved I USB1_ULPI_CLK ULPI link CLK signal 60 MHz clock generated...

Page 381: ...purpose digital input output pin R Function reserved R Function reserved O SD_VOLT1 SD MMC bus voltage select output 1 AI ADC1_0 DAC ADC1 and ADC0 input channel 0 Configure the pin as GPIO input and...

Page 382: ...l purpose digital input output pin R Function reserved O T3_MAT0 Match output 0 of timer 3 I O SD_DAT3 SD MMC data bus line 3 PC_8 N4 2 N PU R Function reserved I O USB1_ULPI_D0 ULPI link bidirectiona...

Page 383: ...line 4 PC_12 L6 2 N PU R Function reserved R Function reserved O U1_DTR Data Terminal Ready output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 R Function...

Page 384: ...R Function reserved I O GPIO6 14 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO4 General purpose digital input output pin PD_1 P1 2 N PU R Function reserve...

Page 385: ...18 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO8 General purpose digital input output pin PD_5 P6 2 N PU R Function reserved O CTOUT_9 SCT output 9 Match...

Page 386: ...22 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO12 General purpose digital input output pin PD_9 T11 84 2 N PU R Function reserved O CTOUT_13 SCT output 13...

Page 387: ...GPIO6 26 General purpose digital input output pin R Function reserved O CTOUT_10 SCT output 10 Match output 3 of timer 3 R Function reserved PD_13 T14 97 2 N PU R Function reserved I CTIN_0 SCT input...

Page 388: ...on reserved I O GPIO6 30 General purpose digital input output pin O SD_VOLT2 SD MMC bus voltage select output 2 O CTOUT_12 SCT output 12 Match output 3 of timer 3 R Function reserved PE_0 P14 106 2 N...

Page 389: ...ose digital input output pin R Function reserved R Function reserved R Function reserved PE_4 K13 120 2 N PU R Function reserved I NMI External interrupt input to NMI R Function reserved I O EMC_A22 E...

Page 390: ...nal memory data line 26 I O GPIO7 7 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_8 F14 150 2 N PU R Function reserved O CTOUT_4 SCT output 4...

Page 391: ...I O EMC_D30 External memory data line 30 I O GPIO7 11 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_12 D15 2 N PU R Function reserved O CTOUT...

Page 392: ...I2C pad O EMC_CKEOUT3 SDRAM clock enable 3 I O GPIO7 15 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PF_0 D12 159 2 O PU I O SSP0_SCK Serial clo...

Page 393: ...ved PF_4 D10 H4 172 120 2 O PU I O SSP1_SCK Serial clock for SSP1 I GP_CLKIN General purpose clock input to the CGU O TRACECLK Trace clock R Function reserved R Function reserved R Function reserved O...

Page 394: ...aster Out Slave in for SSP1 O TRACEDATA 2 Trace data bit 2 I O GPIO7 21 General purpose digital input output pin R Function reserved I O SGPIO6 General purpose digital input output pin I O I2S1_TX_WS...

Page 395: ...unction reserved O U0_TXD Transmitter output for USART0 R Function reserved R Function reserved I O GPIO7 24 General purpose digital input output pin R Function reserved I SD_WP SD MMC card write prot...

Page 396: ...ock output 0 R Function reserved O I2S1_TX_MCLK I2S1 transmit master clock CLK2 D14 K6 141 99 4 O PU O EMC_CLK3 SDRAM clock 3 O CLKOUT Clock output pin R Function reserved R Function reserved I O SD_C...

Page 397: ...icates to the transceiver whether connected as an A device USB0_ID LOW or B device USB0_ID HIGH For OTG this pin has an internal pull up resistor USB0_RREF H1 F3 32 24 8 12 0 k accuracy 1 on board res...

Page 398: ...143 8 I IA I ADC input channel 2 Shared between 10 bit ADC0 1 ADC0_3 ADC1_3 B5 A3 200 139 8 I IA I ADC input channel 3 Shared between 10 bit ADC0 1 ADC0_4 ADC1_4 C6 199 138 8 I IA I ADC input channel...

Page 399: ...F10 F9 L8 L7 E4 E5 F4 135 188 195 82 33 94 131 59 25 Main regulator power supply Tie the VDDREG and VDDIO pins to a common power supply to ensure the same ramp up time for both supply voltages VPP E8...

Page 400: ...ls and hysteresis 5 5 V tolerant pad providing digital I O functions with TTL levels and hysteresis and analog input or output 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V Wh...

Page 401: ...LPC43S2x LPC431x This means that for the parts with shared input channels input ADC0_n is connected to channel n on ADC0 and ADC1 and input ADC1_n is connected to channel n on ADC0 and ADC1 See Table...

Page 402: ...SFS registers control the function of each pin Each pin can support up to eight digital functions Some pins support an additional analog function If the function is GPIO the DIR registers determine w...

Page 403: ...sters 17 3 3 Input buffer To be able to receive a digital signal the input buffer must be enabled through bit EZI in the pin configuration registers see Figure 43 By default the input buffer is disabl...

Page 404: ...ust be enabled for the I2C0 pins SDA and SCL for proper operation 17 3 9 USB1 USB1_DP USB1_DM pins The input signal to the USB1 is controlled by the SFSUSB register Table 195 The USB_ESEA bit in this...

Page 405: ...MISO R R P1_2 GPIO0 9 CTOUT_6 EMC_A7 SGPIO9 R SSP0_MOSI R R P1_3 GPIO0 10 CTOUT_8 SGPIO10 EMC_OE USB0_IND1 SSP1_MISO R SD_RST P1_4 GPIO0 11 CTOUT_9 SGPIO11 EMC_BLS0 USB0_IND0 SSP1_MOSI R SD_VOLT1 P1_5...

Page 406: ...EMC_A9 R R T3_MAT3 R P2_8 SGPIO15 CTOUT_0 U3_DIR EMC_A8 GPIO5 7 R R R P2_9 GPIO1 10 CTOUT_3 U3_BAUD EMC_A0 R R R R P2_10 GPIO0 14 CTOUT_2 U2_TXD EMC_A1 R R R R P2_11 GPIO1 11 CTOUT_5 U2_RXD EMC_A2 R...

Page 407: ...P4_10 R CTIN_2 LCD_VD10 R GPIO5 14 LCD_VD14 R SGPIO15 P5_0 GPIO2 9 MCOB2 EMC_D12 R U1_DSR T1_CAP0 R R P5_1 GPIO2 10 MCI2 EMC_D13 R U1_DTR T1_CAP1 R R P5_2 GPIO2 11 MCI1 EMC_D14 R U1_RTS T1_CAP2 R R P5...

Page 408: ...12 R LCD_VD8 LCD_VD23 TRACEDATA 1 R R ADC0_3 P7_6 GPIO3 14 CTOUT_11 R LCD_LP R TRACEDATA 2 R R P7_7 GPIO3 15 CTOUT_8 R LCD_PWR R TRACEDATA 3 ENET_MDC SGPIO7 ADC1_6 P8_0 GPIO4 0 USB0_PWR_FAU LT R MCI2...

Page 409: ...4 CTIN_5 R R PB_5 R USB1_ULPI_D4 LCD_VD14 R GPIO5 25 CTIN_7 LCD_PWR R PB_6 R USB1_ULPI_D3 LCD_VD13 R GPIO5 26 CTIN_6 LCD_VD19 R ADC0_6 PC_0 R USB1_ULPI_CLK R ENET_RX_CL K LCD_DCLK R R SD_CLK ADC1_1 PC...

Page 410: ...IO12 PD_9 R CTOUT_13 EMC_D23 R GPIO6 23 R R SGPIO13 PD_10 R CTIN_1 EMC_BLS3 R GPIO6 24 R R R PD_11 R R EMC_CS3 R GPIO6 25 USB1_ULPI_D0 CTOUT_14 R PD_12 R R EMC_CS2 R GPIO6 26 R CTOUT_10 R PD_13 R CTIN...

Page 411: ..._1 R R SSP0_SSEL R GPIO7 16 R SGPIO0 R PF_2 R U3_TXD SSP0_MISO R GPIO7 17 R SGPIO1 R PF_3 R U3_RXD SSP0_MOSI R GPIO7 18 R SGPIO2 R PF_4 SSP1_SCK GP_CLKIN TRACECLK R R R I2S0_TX_MCL K I2S0_RX_SC K PF_5...

Page 412: ...le 192 SFSP1_3 R W 0x08C Pin configuration register for pin P1_3 0x00 0xD3 0x00 Table 192 SFSP1_4 R W 0x090 Pin configuration register for pin P1_4 0x00 0xD3 0x00 Table 192 SFSP1_5 R W 0x094 Pin confi...

Page 413: ...0 0xD3 0x00 Table 192 SFSP2_11 R W 0x12C Pin configuration register for pin P2_11 0x00 0xD3 0x00 Table 192 SFSP2_12 R W 0x130 Pin configuration register for pin P2_12 0x00 0xD3 0x00 Table 192 SFSP2_13...

Page 414: ...0 Table 192 SFSP5_3 R W 0x28C Pin configuration register for pin P5_3 0x00 0xD2 0x00 Table 192 SFSP5_4 R W 0x290 Pin configuration register for pin P5_4 0x00 0xD2 0x00 Table 192 SFSP5_5 R W 0x294 Pin...

Page 415: ...0x404 Pin configuration register for pin P8_1 0x00 0x00 0x00 Table 193 SFSP8_2 R W 0x408 Pin configuration register for pin P8_2 0x00 0x00 0x00 Table 193 SFSP8_3 R W 0x40C Pin configuration register f...

Page 416: ...98 0x59C 0x5FC Reserved Pins PC_n SFSPC_0 R W 0x600 Pin configuration register for pin PC_0 0x00 0x00 0x00 Table 192 Table 200 SFSPC_1 R W 0x604 Pin configuration register for pin PC_1 0x00 0x00 0x00...

Page 417: ...r pin PD_14 0x00 0x00 0x00 Table 192 SFSPD_15 R W 0x6BC Pin configuration register for pin PD_15 0x00 0xD8 0x00 Table 192 SFSPD_16 R W 0x6C0 Pin configuration register for pin PD_16 0x00 0xD8 0x00 Tab...

Page 418: ...0x00 0x00 0x00 Table 192 Table 198 SFSPF_9 R W 0x7A4 Pin configuration register for pin PF_9 0x00 0x00 0x00 Table 192 Table 200 SFSPF_10 R W 0x7A8 Pin configuration register for pin PF_10 0x00 0x00 0x...

Page 419: ...P4_0 to P4_10 P5_0 to P5_7 P6_0 to P6_12 P7_0 to P7_7 P8_3 to P8_8 P9_0 to P9_6 PA_0 and PA_4 PB_0 to PB_6 PC_0 to PC_14 PD_0 to PD_16 PE_0 to PE_15 PF_0 to PF_11 ENAIO2 R W 0xC90 Analog function sele...

Page 420: ...cription Reset value Access 2 0 MODE Select pin function 0 R W 0x0 Function 0 default 0x1 Function 1 0x2 Function 2 0x3 Function 3 0x4 Function 4 0x5 Function 5 0x6 Function 6 0x7 Function 7 3 EPD Ena...

Page 421: ...ll down 1 Enable pull down Enable both pull down resistor and pull up resistor for repeater mode 4 EPUN Disable pull up resistor at pad By default the pull up resistor is enabled at reset 0 R W 0 Enab...

Page 422: ...K0 to 0x4008 6C0C SFSCLK3 bit description Bit Symbol Value Description Reset value Access 2 0 MODE Select pin function 0 R W 0x0 Function 0 default 0x1 Function 1 0x2 Function 2 0x3 Function 3 0x4 Fun...

Page 423: ...connected 3 Reserved 4 USB_EPWR Power mode 0 R W 0 Power saving mode Suspend mode 1 Normal mode 5 USB_VBUS Enable the vbus_valid signal This signal is monitored by the USB1 block Use this bit for sof...

Page 424: ...to this bit when using the I2C0 0 R W 0 Disabled 1 Enabled 6 4 Reserved 7 SCL_ZIF Enable or disable input glitch filter for the SCL pin The filter time constant is determined by bit SCL_EFP 0 R W 0 En...

Page 425: ...1 in the ENAIO0 register Table 197 Pins controlled by the ENAIO0 register Pin ADC function ENAIO0 register bit P4_3 ADC0_0 0 P4_1 ADC0_1 1 PF_8 ADC0_2 2 P7_5 ADC0_3 3 P7_4 ADC0_4 4 PF_10 ADC0_5 5 PB_...

Page 426: ...To select the analog function the pad must be set as follows using the corresponding SFSP register 1 Tri state the output driver by selecting an input at the pinmux e g GPIO function in input mode 2...

Page 427: ...ct ADC1_0 0 R W 0 Digital function selected on pin PC_3 1 Analog function ADC1_0 selected on pin PC_3 1 ADC1_1 Select ADC1_1 0 R W 0 Digital function selected on pin PC_0 1 Analog function ADC1_1 sele...

Page 428: ...Set register SFSPF_7 at 0x4008 679C to 0x10 2 Connect the ADC1_7 input to the digital pad Set register ENAIO1at 0x4008 6C8C to 0x80 3 Connect the band gap to the digital pad Set register ENAIO2 at 0x4...

Page 429: ...terrupt Each pin interrupt must be enabled in the NVIC To enable each pin interrupt and configure its edge or level sensitivity use the GPIO pin interrupt registers see Section 19 4 1 Table 203 EMC cl...

Page 430: ...Port 5 0x6 GPIO Port 6 0x7 GPIO Port 7 12 8 INTPIN1 Pint interrupt 1 Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register 0 15 13 PORTSEL1 Pin interrupt 1 Select t...

Page 431: ...lect the port for the pin number to be selected in the INTPIN3 bits of this register 0 0x0 GPIO Port 0 0x1 GPIO Port 1 0x2 GPIO Port 2 0x3 GPIO Port 3 0x4 GPIO Port 4 0x5 GPIO Port 5 0x6 GPIO Port 6 0...

Page 432: ...he PORTSEL6 bit in this register 0 23 21 PORTSEL6 Pin interrupt 6 Select the port for the pin number to be selected in the INTPIN6 bits of this register 0 0x0 GPIO Port 0 0x1 GPIO Port 1 0x2 GPIO Port...

Page 433: ...SCT or the timers Each output of the GIMA is connected to a peripheral function for example a timer capture input or an ADC conversion trigger input and configured through one register which selects t...

Page 434: ...ts that can be selected for this GIMA output For signals that originate from an external pin select a pin from the pinout more than one pins may be possible and program the corresponding pin function...

Page 435: ...e channel 1 pin CTIN_1 USART2 TX active I2S1_RX_MWS pin T2_CAP1 Table 220 10 T2 capture channel 2 pin CTIN_5 USART2 RX active I2S1_TX_MWS pin T2_CAP2 Table 221 11 T2 capture channel 3 SCT output 7 or...

Page 436: ...or example a signal from a pin can be synchronized to the timer branch clock if the pin is connected to the timer capture inputs through the GIMA Even though the timers and the SCT have their own inpu...

Page 437: ...output register setting Description EDGE bit 1 SYNCH bit 2 PULSE bit 3 0 0 0 Asynchronous propagation of the signal from GIMA input to peripheral Use this option when the peripheral can synchronize th...

Page 438: ...223 CAP3_1_IN R W 0x034 Timer 3 CAP3_1 capture input multiplexer GIMA output 13 0 Table 224 CAP3_2_IN R W 0x038 Timer 3 CAP3_2 capture input multiplexer GIMA output 14 0 Table 225 CAP3_3_IN R W 0x03C...

Page 439: ...fset Description Reset value Reference Table 211 Timer 0 CAP0_0 capture input multiplexer CAP0_0_IN address 0x400C 7000 bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0...

Page 440: ..._1 0x1 USART2 TX active 0x2 T0_CAP1 31 8 Reserved Table 212 Timer 0 CAP0_1 capture input multiplexer CAP0_1_IN address 0x400C 7004 bit description Bit Symbol Value Description Reset value Table 213 Ti...

Page 441: ...n 1 Rising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enabl...

Page 442: ...pture input multiplexer CAP1_1_IN address 0x400C 7014 bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 Input inverted 1 EDGE Enable rising edge detection...

Page 443: ...x1 USART0 RX active 0x2 T1_CAP2 31 8 Reserved Table 217 Timer 1 CAP1_2 capture input multiplexer CAP1_2_IN address 0x400C 7018 bit description Bit Symbol Value Description Reset value Table 218 Timer...

Page 444: ...ection 1 Rising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1...

Page 445: ...Description Reset value Table 221 Timer 2 CAP2_2 capture input multiplexer CAP2_2_IN address 0x400C 7028 bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1...

Page 446: ...ut Values 0x3 to 0xF are reserved 0 0x0 CTOUT_7 or T1_MAT3 0x1 T2_CAP3 0x2 T1_MAT3 31 8 Reserved Table 222 Timer 2 CAP2_3 capture input multiplexer CAP2_3_IN address 0x400C 702C bit description Bit Sy...

Page 447: ...ising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enable sin...

Page 448: ...scription Reset value Table 226 Timer 3 CAP3_3 capture input multiplexer CAP3_3_IN address 0x400C 703C bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 In...

Page 449: ...input Values 0x3 to 0xF are reserved 0 0x0 CTIN_0 0x1 SGPIO3 0x2 SGPIO3_DIV 31 8 Reserved Table 227 SCT CTIN_0 capture input multiplexer CTIN_0_IN address 0x400C 7040 bit description Bit Symbol Value...

Page 450: ...ion 1 Rising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Ena...

Page 451: ...pture input multiplexer CTIN_4_IN address 0x400C 7050 bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 Input inverted 1 EDGE Enable rising edge detection...

Page 452: ...2 RX active 0x2 SGPIO12_DIV 31 8 Reserved Table 232 SCT CTIN_5 capture input multiplexer CTIN_5_IN address 0x400C 7054 bit description Bit Symbol Value Description Reset value Table 233 SCT CTIN_6 cap...

Page 453: ...ection 1 Rising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1...

Page 454: ...e 235 ADCHS trigger input multiplexer ADCHS_TRIGGER_IN address 0x400C 7060 bit description continued Bit Symbol Value Description Reset value Table 236 Event router input 13 multiplexer EVENTROUTER_13...

Page 455: ...ynchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enable single pulse generation 7 4 SELECT Select input...

Page 456: ...onization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enable single pulse generation 7 4 SELECT Select input Value...

Page 457: ...errupts must be enabled in the NVIC see Table 78 The GPIO group interrupts must be enabled in the NVIC see Table 78 GPIO port registers can be accessed by the GPDMA as memory to memory transfer UM1050...

Page 458: ...ured as input or output by software All GPIO pins default to inputs with interrupt disabled at reset Pin registers allow pins to be sensed and set individually 19 4 General description The GPIO pins c...

Page 459: ...Rev 2 1 10 December 2015 459 of 1441 NXP Semiconductors UM10503 Chapter 19 LPC43xx LPC43Sxx GPIO 19 4 3 GPIO port The GPIO port registers can be used to configure each GPIO pin as input or output and...

Page 460: ...ters bits that are not shown are reserved Table 243 Register overview GPIO pin interrupts base address 0x4008 7000 Name Access Address offset Description Reset value Reference ISEL R W 0x000 Pin Inter...

Page 461: ...Description Reset value Reference Table 245 Register overview GPIO GROUP1 interrupt base address 0x4008 9000 Name Access Address offset Description Reset value Reference CTRL R W 0x000 GPIO grouped i...

Page 462: ...e 261 W128 to W159 R W 0x1200 to 0x12FC Word pin registers port 4 ext 1 word 32 bit Table 261 W160 to W191 R W 0x1280 to 0x12FC Word pin registers port 5 ext 1 word 32 bit Table 261 W192 to W223 R W 0...

Page 463: ...2 R W 0x2208 Write Set register for port 2 Read output bits for port 2 0 word 32 bit Table 266 SET3 R W 0x220C Write Set register for port 3 Read output bits for port 3 0 word 32 bit Table 266 SET4 R...

Page 464: ...t is enabled If the pin interrupt mode is level sensitive PMODE 1 the level interrupt is enabled The IENF register configures the active level HIGH or LOW for this interrupt NOT5 WO 0x2314 Toggle port...

Page 465: ...is level sensitive PMODE 1 the level interrupt is cleared 19 5 1 5 Pin interrupt active level falling edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn register...

Page 466: ...ding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register If the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is cleared If the pin i...

Page 467: ...active level falling edge interrupt clear register CIENF address 0x4008 7018 bit description Bit Symbol Description Reset value Access 7 0 CENAF Ones written to this address clears bits in the IENF th...

Page 468: ...256 Pin interrupt status register IST address 0x4008 7024 bit description Bit Symbol Description Reset value Access 7 0 PSTAT Pin interrupt status Bit n returns the status clears the edge interrupt o...

Page 469: ...or write words to sense or set the state of four pins Remark To read the signal on the GPIO input enable the input buffer in the syscon block for the corresponding pin see Table 192 to Table 194 Tabl...

Page 470: ...in see Table 192 to Table 194 19 5 3 3 GPIO port direction registers Each GPIO port n n 0 to 7 has one direction register for configuring the port pins as inputs or outputs Table 260 GPIO port byte pi...

Page 471: ...of the corresponding MASK register and writing to one of these registers only affects output register bits that are enabled by zeros in the corresponding MASK register Table 263 GPIO port mask regist...

Page 472: ...state of all GPIO pins except those selected for analog input or output in the I O Configuration logic A pin does not have to be selected for GPIO in I O Configuration in order to read its state There...

Page 473: ...register loads the output bit with the OR of all of the bits written This feature follows the definition of truth of a multi bit value in programming languages Writing to a port s PORT register loads...

Page 474: ...s PINTSEL0 7 All registers in the pin interrupt block contain 8 bits corresponding to the pins called out by the PINTSEL0 7 registers The ISEL register defines whether each interrupt pin is edge or le...

Page 475: ...wing lists some recommended uses for using the GPIO port registers For initial setup after Reset or re initialization write the PORT registers To change the state of one pin write a Byte Pin or Word P...

Page 476: ...an trigger the 12 bit ADC SGPIO output pins SGPIO14 and SGPIO15 can trigger a GPDMA request see Section 20 7 6 20 3 Features Each SGPIO input output slice can be used to perform a serial to parallel o...

Page 477: ...can be shifted at a time n 1 2 4 or 8 for serial dual serial quad serial and byte parallel IO Clock 12 bit counter running at SGPIO_CLOCK creates a shift clock to capture input or create output values...

Page 478: ...20 4 2 Interrupts The combined SGPIO interrupt is connected to the Cortex M4 interrupt 31 see Table 78 and the Cortex M0 NVIC 19 On parts with enabled Cortex M0 subsystem each SGPIO interrupt has a se...

Page 479: ...NXP B V 2015 All rights reserved User manual Rev 2 1 10 December 2015 479 of 1441 NXP Semiconductors UM10503 Chapter 20 LPC43xx LPC43Sxx Serial GPIO SGPIO 20 5 Pin description Table 271 SGPIO pin desc...

Page 480: ...e COUNT0 reaches 0x0 POS counts down 0 Table 283 MASK_A R W 0x0200 Mask for pattern match function of slice A 0 Table 284 MASK_H R W 0x0204 Mask for pattern match function of slice H 0 Table 285 MASK_...

Page 481: ...which pins Note that for modes wider than 1 bit the output enable is defined by 2 bits one bit for the LSB and one bit for the MSBs When using wider than 1 bit modes P_OE_CFG dout_oem2 dout_oem4 or d...

Page 482: ...8a 8 bit mode 8a 0xA dout_doutm8b 8 bit mode 8b 0xB dout_doutm8c 8 bit mode 8c 6 4 P_OE_CFG Output enable source All other values are reserved 0 R W 0x0 gpio_oe state set by GPIO_OEREG 0x4 dout_oem1 1...

Page 483: ...multiplexing SGPIO pin Output mode register OUT_MUX_CFG bits P_OUT_CFG see Table 273 1011 1010 1001 0111 0110 0101 0011 0010 0001 0000 1000 0100 8 bit 8c 8 bit 8b 8 bit 8a 4 bit 4c 4 bit 4b 4 bit 4a...

Page 484: ...on slices that can be a clock source for other slices cannot support external slice clocks themselves CLK_SOURCE_SLICE_MODE These slices should not feed a clock higher than SGPIO_CLOCK 2 to the other...

Page 485: ...s register 0x3 External SGPIO pin SGPIO8 SGPIO9 SGPIO10 or SGPIO11 8 7 QUALIFIER_PIN_M ODE Select qualifier pin 0 R W 0x0 SGPIO8 0x1 SGPIO9 0x2 SGPIO10 0x3 SGPIO11 10 9 QUALIFIER_ SLICE_MODE Select qu...

Page 486: ...P support matching with a mask register MASK_x For other slices the pattern is not masked Bit CLKGEN_MODE selects as shift clock the clock generated by the slice counter or by an external pin or othe...

Page 487: ...the match filter is active or whether data is captured 0 R W 0x0 Do not match data 0x1 Match data 1 CLK_CAPTURE_ MODE Capture clock mode 0 R W 0x0 Use rising clock edge 0x1 Use falling clock edge 2 CL...

Page 488: ...erated slice shift clock frequency frequency shift_clock frequency SGPIO_CLK PRESET 1 20 6 7 Down counter registers This status register reflect the slice shift clock counter value If the counter has...

Page 489: ...10 Slice H mask register Table 282 Down counter registers COUNT 0 15 addresses 0x4010 1180 COUNT0 to 0x4010 11BC COUNT15 bit description Bit Symbol Description Reset value Access 11 0 COUNT Down coun...

Page 490: ...tch function of slice I 0 No effect 1 Mask this bit 0 R W Table 287 Slice P mask register MASK_P address 0x4010 120C bit description Bit Symbol Description Reset value Access 31 0 MASK_P Mask for patt...

Page 491: ...is register clears the shift clock interrupt mask of a slice Table 290 GPIO output enable register GPIO_OENREG address 0x4010 1218 bit description Bit Symbol Description Reset value Access 15 0 GPIO_O...

Page 492: ...n Bit Symbol Description Reset value Access 15 0 CLR_SCI 1 Shift clock interrupt clear mask of slice n 0 W 31 16 Reserved Table 294 Shift clock interrupt set mask register SET_EN_0 address 0x4010 1F04...

Page 493: ...is register can be read at any time but can only be changed by writing to the corresponding bits in the SET_EN_1 or CLR_EN_1 registers Table 298 Shift clock interrupt set status register SET_STATUS_0...

Page 494: ...us register STATUS_1 address 0x4010 1F2C bit description Bit Symbol Description Reset value Access 15 0 STATUS_CCI Exchange clock interrupt status of slice n 0 R 31 16 Reserved Table 303 Exchange cloc...

Page 495: ...Reserved Table 308 Pattern match interrupt status register STATUS_2 address 0x4010 1F4C bit description Bit Symbol Description Reset value Access 15 0 STATUS_PMI Match interrupt status of slice n 0 R...

Page 496: ...slice n 0 W 31 16 Reserved Table 313 Input interrupt enable register ENABLE_3 address 0x4010 1F68 bit description Bit Symbol Description Reset value Access 15 0 ENABLE3_INPI Input interrupt enable of...

Page 497: ...and vice versa One slice contains 32 1 bit registers REG connected in a chain Data is right shifted through the chain Input data is shifted in at the MSB and shifted out from the LSB All input data w...

Page 498: ...ing DOUT with bit REG 0 Thus COUNT controls the serial data rate When several slices are used to create an interface port the phase between the different slices can be controlled by using different in...

Page 499: ...es are concatenated this field should be set the same for all involved slices Field CONCAT_ORDER sets the concatenation size For a size of zero the self loop mode the slice output is routed back to th...

Page 500: ...pped with REG when POS reaches zero The MATCH_MODE bit must be set to 1 The input data is now compared to the programmed pattern When a match is found the pattern match interrupt is raised E external...

Page 501: ...by register SGPIO_MUX_CFG The 16 slices are denoted as A to P A suffix indicates which slice bit connects to a pin e g in 8 bit parallel input mode pins SGPIO0 to 7 connect to slice A bits 24 31 Not a...

Page 502: ...SGPIO6 A30 C30 F30 F31 SGPIO7 A31 C31 F31 L31 SGPIO8 B31 B28 B30 B31 xcl xq SGPIO9 B30 B29 B31 M31 xcl xq 00 01 10 clk_qualifier qua li f i e r_ p i n _mod e 11 0 10 9 00 01 10 11 qualifier _slice A D...

Page 503: ...q SGPIO12 B27 D28 D30 D31 SGPIO13 B26 D29 D31 O31 SGPIO14 B25 D30 H30 H31 SGPIO15 B24 D31 H31 P31 Table 317 Slice I O multiplexing x external cl clock q qualifier SGPIO Pin Input mode Parallel mode 8...

Page 504: ...led slave clock MCK is needed use a slice that is capable to create clocks for other slices D H O or P e g use slice D In slave mode MCK is an input MCK is divided down to create the shift clock for D...

Page 505: ...wn in Table 320 In Master mode the shift clocks are generated by the local slice COUNTERs The WS and CK slices contain repeating patterns and are concatenated in self loop mode The data width is 1 bit...

Page 506: ...lock for the SD and WS signals MCK is not used The slice settings that are different for slave mode 1 with SCK supplied at pin 8 are shown in Table 324 Table 322 SGPIO setting for I2S 5 1 SLICE_MUX_CF...

Page 507: ...ert the clock phase use patterns 0xAAAA AAAA instead MCK is not phase aligned to the other I2S signals To toggle the output set REG3 0x5555 5555 and REG_SS3 0x5555 5555 In slave mode MCK should be div...

Page 508: ...falling edge From pins SGPIO8 SGPIO11 which can be used as clock input choose pin SGPIO8 HSCYNC is used as qualifier for input data Pins SGPIO8 SGPIO11 can be used as qualifier pin SGPIO8 is already...

Page 509: ...M by writing CTRL_ENABLE 0x1F3F Data is captured at a falling PIXCLK when HSYNC is low At a POS interrupt 32 data words are read from REG_SS and written to the data SRAM Then SGPIO15 is toggled to re...

Page 510: ...e DMA Controller can assert either a burst DMA request or a single DMA request The DMA burst size is set by programming the DMA Controller Memory to memory memory to peripheral peripheral to memory an...

Page 511: ...ontroller allows peripheral to memory memory to peripheral peripheral to peripheral and memory to memory transactions Each DMA stream provides unidirectional serial DMA transfers for a single source a...

Page 512: ...h 0 0x1 USART0 transmit 0x2 Reserved Reserved 0x3 Reserved AES in 2 0x0 Timer0 match 1 0x1 USART0 receive 0x2 Reserved Reserved 0x3 Reserved AES out 3 0x0 Timer1 match 0 0x1 UART1 transmit 0x2 I2S1 DM...

Page 513: ...ilable request signals are BREQ 15 0 Burst request signals These cause a programmed burst number of data to be transferred 9 0x0 SSP0 receive SSP0 receive 0x1 I2S0 DMA request 1 0x2 SCT DMA request 1...

Page 514: ...the operation of that channel Other registers controls aspects of how source peripherals relate to the DMA Controller There are also global DMA control and status registers Table 332 Register overview...

Page 515: ...s SRCADDR3 R W 0x160 DMA Channel 3 Source Address Register 0x0000 0000 Table 347 DESTADDR3 R W 0x164 DMA Channel 3 Destination Address Register 0x0000 0000 Table 348 LLI3 R W 0x168 DMA Channel 3 Linke...

Page 516: ...Table 348 LLI7 R W 0x1E8 DMA Channel 7 Linked List Item Register 0x0000 0000 Table 349 CONTROL7 R W 0x1EC DMA Channel 7 Control Register 0x0000 0000 Table 350 CONFIG7 R W 0x1F0 DMA Channel 7 Configur...

Page 517: ...ts When writing to this register each data bit that is HIGH causes the corresponding bit in the status register to be cleared Data bits that are LOW have no effect on the corresponding bit in the regi...

Page 518: ...description Bit Symbol Description Reset value Access 7 0 INTERRCLR Writing a 1 clears the error interrupt request IntErrStat for DMA channels Each bit represents one channel 0 writing 0 has no effect...

Page 519: ...not used at the same time 21 6 10 DMA Software Single Request Register The SOFTSREQ Register is read write and enables DMA single transfer requests to be generated by software A DMA request can be gen...

Page 520: ...ter bit A register bit is cleared when the transaction has completed Reading the register indicates which sources are requesting last single DMA transfers A request can be generated from either a peri...

Page 521: ...or a particular group of DMA requests This register is reset to 0 enabling the synchronization logic by default Table 344 DMA Software Last Single Request Register SOFTLSREQ address 0x4000 202C bit de...

Page 522: ...ansferred Reading the register when the channel is active does not provide useful information This is because by the time software has processed the value read the address may have progressed It is in...

Page 523: ...ers associated with it are completed Programming this register when the DMA channel is enabled may have unpredictable side effects 21 6 19 DMA channel control registers The eight read write CONTROL Re...

Page 524: ...ze value is not used if the DMA Controller is not the flow controller 0x0 R W 14 12 SBSIZE Source burst size Indicates the number of transfers that make up a source burst This value must be set to the...

Page 525: ...Remark Only Master1 can access a peripheral Master0 can only access memory 0 R W 0 AHB Master 0 selected for destination transfer 1 AHB Master 1 selected for destination transfer 26 SI Source increme...

Page 526: ...Access Table 351 DMA Channel Configuration registers CONFIG 0 7 0x4000 2110 CONFIG0 to 0x4000 21F0 CONFIG7 bit description Bit Symbol Value Description Reset value Access 0 E Channel enable Reading th...

Page 527: ...SP1 transmit 0x4 Timer1 match 1 UART1 receive I2S1 DMA request 2 SSP1 receive 0x5 Timer2 match 0 USART2 transmit SSP1 transmit SGPIO15 0x6 Timer2 match 1 USART2 receive SSP1 receive SGPIO14 0x7 Timer3...

Page 528: ...AES in SSP1 receive USART3 receive 0xE ADC1 AES out SSP1 transmit USART3 transmit 0xF DAC SCT match 3 SGPIO15 Timer3 match 0 13 11 FLOWCNTRL Flow control and transfer type This value indicates the flo...

Page 529: ...52 lists the bit values of the three flow control and transfer type bits identified in Table Table 351 17 A Active 0 there is no data in the FIFO of the channel 1 the channel FIFO has data This value...

Page 530: ...The register block stores data written or to be read across the AHB interface 21 7 1 3 DMA request and response interface See DMA Interface description for information on the DMA request and response...

Page 531: ...avior Source endian Destination endian Source width Destination width Source transfer no byte lane Source data Destination transfer no byte lane Destination data Little Little 8 8 1 7 0 2 15 8 3 23 16...

Page 532: ...34 56 78 1 31 0 12345678 Big Big 16 8 1 31 24 1 23 16 2 15 8 2 7 0 12 34 56 78 1 31 24 2 23 16 3 15 8 4 7 0 12121212 34343434 56565656 78787878 Big Big 16 16 1 31 24 1 23 16 2 15 8 2 7 0 12 34 56 78 1...

Page 533: ...es the number of transfers delegated to the master interface by the lower priority channel before switching over to transfer data for the higher priority channel In the worst case this is as large as...

Page 534: ...ar the channel enable bit in the relevant channel configuration register 21 8 1 5 Setting up a new DMA transfer To set up a new DMA transfer If the channel is not set aside for the DMA transaction 1 R...

Page 535: ...e transfer has finished 2 A TC interrupt is generated if enabled 3 The DMA Controller moves on to the next LLI The following sections describe the DMA Controller data flow sequences for the four allow...

Page 536: ...quence ends 21 8 2 2 Peripheral to peripheral DMA flow For a peripheral to peripheral DMA flow the following sequence occurs 1 Program and enable the DMA channel 2 Wait for a source DMA request 3 The...

Page 537: ...riority otherwise other DMA channels cannot access the bus until the memory to memory transfer has finished or other AHB masters cannot perform any transaction 21 8 3 Interrupt requests Interrupt requ...

Page 538: ...er does not support AHB INCR4 or INCR8 bursts using halfword or byte transfer size Start address in SDRAM should always be aligned to a burst boundary address 21 8 4 1 Word aligned transfers across a...

Page 539: ...el 7 the lowest priority 3 Write the first linked list item previously written to memory to the relevant channel in the DMA Controller 4 Write the channel configuration information to the channel Conf...

Page 540: ...Source start address 0x2000 B200 Destination address set to the destination peripheral address Transfer width word 32 bit Transfer size 3072 bytes 0xC00 Fig 55 LLI example LLI 1 Source address Destin...

Page 541: ...into the DMA Controller When the first packet of data has been transferred the next LLI is automatically loaded The final LLI is stored at 0x2000 0070 and contains Source start address 0x2000 1200 De...

Page 542: ...ommands CE ATA digital protocol commands Command Completion signal and interrupt to processor Completion Signal disable feature One SD or MMC 4 4 or CE ATA 1 1 device CRC generation and error detectio...

Page 543: ...SD MMC block diagram Registers FIFO Control DMA Interface Control BIU Clock Control FIFO RAM Interrupts status APB AHB Slave Synchronizer Output Hold Register Card Socket Regulators Power Switches ccl...

Page 544: ...value Reference CTRL R W 0x000 Control Register 0 Table 358 PWREN R W 0x004 Power Enable Register 0 Table 359 CLKDIV R W 0x008 Clock Divider Register 0 Table 360 CLKSRC R W 0x00C SD Clock Source Regis...

Page 545: ...0000 Table 390 DATA R W 0x100 Data FIFO read write if address is equal or greater than 0x100 then FIFO is selected as long as device is selected Address 0x100 and above are mapped to the data FIFO Mor...

Page 546: ...e bus and returns to idle state 0 0 No change 1 Send auto IRQ response 8 ABORT_READ_DATA Abort read data Used in SDIO card suspend sequence 0 0 No change 1 Abort After suspend command is issued during...

Page 547: ...INTERRUPT _STATUS CEATA device interrupt status Software should appropriately write to this bit after power on reset or any other reset to CE ATA device After reset usually CE ATA device interrupt is...

Page 548: ...e of ff means divide by 2 255 510 and so on 0 15 8 CLK_DIVIDER1 Clock divider 1 value Clock division is 2 n For example value of 0 means divide by 2 0 0 no division bypass value of 1 means divide by 2...

Page 549: ...0 4010 bit description Bit Symbol Description Reset value 0 CCLK_ENABLE Clock enable control for SD card clock One MMC card clock supported 0 Clock disabled 1 Clock enabled 0 15 1 Reserved 16 CCLK_LOW...

Page 550: ...lue 15 0 BLOCK_SIZE Block size 0x200 31 16 Reserved Table 366 Byte Count Register BYTCNT address 0x4000 4020 bit description Bit Symbol Description Reset value 31 0 BYTE_COUNT Number of bytes to be tr...

Page 551: ...Volt_switch_int Bits used to mask unwanted interrupts Value of 0 masks interrupt value of 1 enables interrupt 0 11 FRUN FIFO underrun overrun error Bits used to mask unwanted interrupts Value of 0 ma...

Page 552: ...d write Don t care if no data expected from card 0 0 Read from card 1 Write to card 11 TRANSFER_MODE Transfer mode Don t care if no data expected 0 0 Block data transfer command 1 Stream data transfer...

Page 553: ...nd initialization sequence before sending this command 20 16 Reserved Always write as 0 0 21 UPDATE_CLOCK_ REGISTERS_ONLY Update clock registers only Following register values transferred into card cl...

Page 554: ...ing the CMD line low Do NOT set disable_boot and enable_boot together 0 25 EXPECT_BOOT_ACK Expect Boot Acknowledge When Software sets this bit along with enable_boot CIU expects a boot acknowledge sta...

Page 555: ...le 373 Response Register 3 RESP3 address 0x4000 403C bit description Bit Symbol Description Reset value 31 0 RESPONSE3 Bit 127 96 of long response 0 Table 374 Masked Interrupt Status Register MINTSTS...

Page 556: ...es interrupt 0 masks interrupt 0 No SDIO interrupt from card 1 SDIO interrupt from card In MMC Ver3 3 only mode this bit is always 0 31 17 Reserved Table 374 Masked Interrupt Status Register MINTSTS a...

Page 557: ...ss of interrupt mask status Volt_switch_int 0 11 FRUN FIFO underrun overrun error Writes to bits clear status bit Value of 1 clears status bit and value of 0 leaves bit intact Bits are logged regardle...

Page 558: ...end bit 14 Cmd path wait NCC 15 Wait CMD to response turnaround NOTE The command FSM state is represented using 19 bits The STATUS Register 7 4 has 4 bits to represent the command FSM states Using th...

Page 559: ...O count of status register which is 13 bits Limitation TX_WMark 1 Recommended value TX_WMARK 16 means less than or equal to FIFO_DEPTH 2 0 15 12 Reserved 0 27 16 RX_WMARK FIFO threshold watermark leve...

Page 560: ...1 TX_WMARK 1 15 MSize 4 TX_WMark 8 MSize 4 TX_WMark 4 MSize 4 TX_WMark 12 MSize 8 TX_WMark 8 MSize 8 TX_WMark 4 Allowed combinations for MSize and RX_WMark are MSize 1 RX_WMARK 0 14 MSize 4 RX_WMark 3...

Page 561: ...transfer completes during data transfer register returns 0 0 Table 381 Transferred Host to BIU FIFO Byte Count Register TBBCNT address 0x4000 4060 bit description Bit Symbol Description Reset value 31...

Page 562: ...ly for dual buffer structure DSL is read write 0 7 DE SD MMC DMA Enable When set the SD MMC DMA is enabled DE is read write 10 8 PBL Programmable Burst Length These bits indicate the maximum number of...

Page 563: ...r occurred IDSTS 12 10 When this bit is set the DMA disables all its bus accesses Writing a 1 clears this bit 0 3 Reserved 4 DU Descriptor Unavailable Interrupt This bit is set when the descriptor is...

Page 564: ...Table 387 Internal DMAC Status Register IDSTS address 0x4000 408C bit description Bit Symbol Description Reset value Table 388 Internal DMAC Interrupt Enable Register IDINTEN address 0x4000 4090 bit...

Page 565: ...a single power supply sourcing the card slot 8 NIS Normal Interrupt Summary Enable When set a normal interrupt is enabled When reset a normal interrupt is disabled This bit enables the following bits...

Page 566: ...rd Type Transfer Type Byte Count SEND_AUTO_ STOP bit set Comments MMC Stream read 0 No Open ended stream MMC Stream read 0 Yes Auto stop after all bytes transfer MMC Stream read 0 No Open ended stream...

Page 567: ...is less than 6 48 bits the data path transmits the data last in order to meet the above condition Multiple block read memory for SD card with byte count greater than 0 If the block size is less than...

Page 568: ...ng from a card the Data Transfer Over RINTSTS 3 interrupt occurs as soon as the data transfer from the card is over There still could be some data left in the FIFO and the RX_WMark interrupt may or ma...

Page 569: ...the following 1 After power on reset configure the SD MMC pins using the SFSP registers in the syscon block Table 191 2 Set masks for interrupts by clearing appropriate bits in the Interrupt Mask regi...

Page 570: ...is 400 KHz and use the following enumeration command sequence SD card Send CMD0 ACMD41 CMD2 CMD3 SDHC card send CMD0 SDCMD8 ACMD41 CMD2 CMD3 SDIO Send CMD5 if the function count is valid CMD3 For the...

Page 571: ...te parameters Using these two registers the Module forms the command and sends it to the command bus The Module reflects the errors in the command response through the error bits of the RINTSTS regist...

Page 572: ...s not busy and is in a transfer state which can be done using the CMD13 and CMD7 commands respectively Table 392 CMD register settings for No Data Command Name Value Comment start_cmd 1 update_clock_...

Page 573: ...full condition the Module cannot continue with data transfer The clock to the card has been stopped 5 Data read time out error bit 9 Card has not sent data within the time out period 6 Data CRC error...

Page 574: ...ead Name Value Comment start_cmd 1 update_clock_ registers_only 0 No clock parameters update command card_number 0 Card number in use Only zero is possible because one card is support Data_expected 1...

Page 575: ...t conditions from data starvation by the cpu In both cases the software should write data into the FIFO 8 When a Data_Transfer_Over interrupt is received the data command is over For an open ended blo...

Page 576: ...nsfer the Module sends the STOP command Completion of this AUTO_STOP command is reflected by the Auto_command_done interrupt A response to an AUTO_STOP is stored in the RESP1 register 0x34 A stream tr...

Page 577: ...Without Response Sequence Program the CMDARG register 0x28 with the appropriate command argument parameters listed in Table 395 Program the Command register using the command index as CMD52 Similar t...

Page 578: ...END command The Module then resets the data state machine and comes out of the wait state To accomplish this set abort_read_data bit 8 in the Control register Wait for data completion Get pending byte...

Page 579: ...ta transfer commands For information on the basic settings and interrupts generated for different conditions refer to Data Transfer Commands 22 7 5 2 1 Reset and Device Recovery Before starting CE ATA...

Page 580: ...s command involves data transfer between the CE ATA device and the Module To send a data command the Module needs a command argument total data size and block size Software can receive or send data th...

Page 581: ...not expected Read_ceata_device 0 1 1 If RW_BLK or RW_REG read update_clock_ registers_only 0 No clock parameters update command card_number 0 Card number in use Only zero is possible because one card...

Page 582: ...write or 0 read 30 24 Reserved 0 23 16 Reserved 0 15 8 Data Count Unit 15 8 Data count 1 0 Data Count Unit 7 0 Data count Table 402 CMD register settings Name Value Comment start_cmd 1 Css_expect 1 Co...

Page 583: ...f time out happened while waiting for Command Completion Signal CCS the cpu needs to send Command Completion Signal Disable CCSD followed by a STOP command to abort the pending ATA command The cpu can...

Page 584: ...cleared to 0 BLKSIZ register bits 15 0 and BYTCNT register Set to 16 The cpu controller uses the following settings for data retrieval RW_BLK CMD register settings ccs_expect set to 1 data_expected se...

Page 585: ...rved fields of the task file cleared to 0 BLKSIZ register bits 15 0 and BYTCNT register Set to 16 22 7 5 3 Controller DMA FIFO Reset Usage Communication with the card involves the following Controller...

Page 586: ...either retry the whole data transfer again or retry from a specified block onwards By reading the contents of the TCBCNT later the software can decide how many bytes remain to be copied Response error...

Page 587: ...ock data transfer if a negative CRC status is received from the device the data path signals a data CRC error to the BIU by setting the data CRC error bit in the RINTSTS register It then continues fur...

Page 588: ...gister IDSTS for the data that ends in the buffer pointed to by this descriptor 2 LD Last Descriptor When set this bit indicates that the buffers pointed to by this descriptor are the last buffers of...

Page 589: ...icates that the descriptor is owned by the SD MMC DMA When this bit is reset it indicates that the descriptor is owned by the Host The SD MMC DMA clears this bit when it completes the data transfer Ta...

Page 590: ...he start address and the number of transfers required to the AHB Master Interface When the AHB Interface is configured for fixed length bursts then it transfers data using the best combination of INCR...

Page 591: ...be accessed using a burst SINGLE transfers are performed on AHB Master Interface 8 The SD MMC DMA fetches the Transmit data from the data buffer in the Host memory and transfers to the FIFO for trans...

Page 592: ...y writing a 1 to the corresponding bit position When all the enabled interrupts within a group are cleared the corresponding summary bit is cleared When both the summary bits are cleared the interrupt...

Page 593: ...IFO overflow underflow can result For example consider the following scenarios For transmit PBL 4 Tx watermark 1 For these programming values if the FIFO has only one location empty it issues a dw_dma...

Page 594: ...all four SFSCLKn registers in the SCU The EMC is reset by the EMC_RST reset 21 UM10503 Chapter 23 LPC43xx LPC43Sxx External Memory Controller EMC Rev 2 1 10 December 2015 User manual Table 410 EMC pi...

Page 595: ...elay Output enable and write enable delays Extended wait 16 bit and 32 bit wide chip select SDRAM memory support with up to four chip selects and up to 256 MB of data Controller supports 2 kbit 4 kbit...

Page 596: ...ntroller peripheral offering support for asynchronous static memory devices such as RAM ROM and Flash as well as dynamic memories such as Single Data Rate SDRAM The EMC has four ports that connect to...

Page 597: ...tion 3 6 AHB Multilayer matrix configuration 23 5 Memory bank select Eight independently configurable memory chip selects are supported Pins EMC_CS3 to EMC_CS0 are used to select static memory devices...

Page 598: ...mic 256 MB Table 412 Memory bank selection Chip select pin Address range Memory type Size of range Table 413 EMC pin description Pin function Direction Description EMC_A 23 0 O Address bus EMC_D 31 0...

Page 599: ...8 Selects the active to active command period 0x1F 0x1F Table 427 DYNAMICRFC R W 0x04C Selects the auto refresh period 0x1F 0x1F Table 428 DYNAMICXSR R W 0x050 Selects the exit self refresh to active...

Page 600: ...ICWAITRD0 R W 0x20C Selects the delay from chip select 0 to a read access 0x1F 2 0xE Table 439 STATICWAITPAGE0 R W 0x210 Selects the delay for asynchronous page mode sequential accesses for chip selec...

Page 601: ...Table 439 STATICWAITPAGE2 R W 0x250 Selects the delay for asynchronous page mode sequential accesses for chip select 2 0x1F 0x1F Table 440 STATICWAITWR2 R W 0x254 Selects the delay from chip select 2...

Page 602: ...ory areas Clearing the M bit enables CS0 and DYCS0 memory to be accessed 1 0 Normal Normal memory map 1 Reset Reset memory map Static memory CS1 is mirrored onto CS0 and DYCS0 POR reset value 2 L Low...

Page 603: ...er software should not write ones to reserved bits The value read from a reserved bit is not defined Table 416 EMC Status register STATUS address 0x4000 5004 bit description Bit Symbol Value Descripti...

Page 604: ...LKOUT stops when all SDRAMs are idle and during self refresh mode 1 Run CLKOUT runs continuously POR reset value 2 SR Self refresh request EMC SREFREQ By writing 1 to this bit self refresh can be ente...

Page 605: ...being clocked run from the IRC oscillator at 12 MHz The IRC oscillator frequency must be used as the EMC_CCLK rate for refresh calculations if auto refresh through warm reset is requested Note The ref...

Page 606: ...used for all four dynamic memory chip selects Therefore the worst case value for all of the chip selects must be programmed Table 420 Dynamic Memory Read Configuration register DYNAMICREADCONFIG addre...

Page 607: ...th one wait state Note This register is used for all four dynamic memory chip selects Therefore the worst case value for all of the chip selects must be programmed 23 7 11 Dynamic Memory Data In to Ac...

Page 608: ...led mode This value is normally found in SDRAM data sheets as tRC This register is accessed with one wait state Note This register is used for all four dynamic memory chip selects Therefore the worst...

Page 609: ...register is used for all four dynamic memory chip selects Therefore the worst case value for all of the chip selects must be programmed 23 7 16 Dynamic Memory Active Bank A to Active Bank B Time regis...

Page 610: ...tstanding transactions However if necessary these control bits can be altered during normal operation This register is accessed with one wait state Table 430 Dynamic Memory Active Bank A to Active Ban...

Page 611: ...AMICCONFIG0 to 0x4000 5160 DYNAMICCONFIG3 bit description Bit Symbol Value Description Reset value 2 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit...

Page 612: ...1 01 64 Mb 4Mx16 4 banks row length 12 column length 8 0 1 010 00 128 Mb 16Mx8 4 banks row length 12 column length 10 0 1 010 01 128 Mb 8Mx16 4 banks row length 12 column length 9 0 1 011 00 256 Mb 32...

Page 613: ...nt or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode These registers are accessed with one wait state Note The values progra...

Page 614: ...CLK cycles 0x3 Three EMC_CCLK cycles POR reset value 7 2 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 9 8 CAS CAS latency 11 0x0 Rese...

Page 615: ...n signal LOW For reads all the UB and LB signals must be asserted LOW so that the bus is driven In this case the byte lane state PB bit must be HIGH Remark When PB is set to 0 the WE signal is undefin...

Page 616: ...from the chip select to the read access It is recommended that these registers are modified during system initialization or when there are no current or outstanding transactions This can be ensured by...

Page 617: ...g register These registers are accessed with one wait state Table 439 Static Memory Read Delay registers STATICWAITRD 0 3 address 0x4000 520C STATICWAITRD0 to 0x4000 526C STATICWAITRD3 bit description...

Page 618: ...ry banks Bus turn around cycles prevent bus contention on the external memory data bus Table 441 Static Memory Write Delay registers STATICWAITWR 0 3 address 0x4000 5214 STATICWAITWR0 to 0x4000 5274 S...

Page 619: ...ility of endianness problems all data transfers to and from the registers of the EMC must be 32 bits wide Note If an access is attempted with a size other than a word 32 bits it causes an ERROR respon...

Page 620: ...are used to Merge write transactions so that the number of external transactions are minimized Buffer data until the EMC can complete the write transaction improving AHB write latency Convert all dyna...

Page 621: ...in a buffer the LRU buffer is selected If the buffer is dirty contains write data the write data is flushed to memory When an empty buffer is available the read command is posted to the memory A buffe...

Page 622: ...is loads the mode register with the correct settings Table 443 SDRAM mode register description Address line SDRAM mode register bit Value Description A2 A0 2 0 Burst length 000 1 M3 0 1 M3 1 001 2 M3...

Page 623: ...e number of bits needed to indicate the number of banks Most SDRAM devices use 2 bank select bits for four banks Select the SDRAM memory mapped address DYCSX The SDRAM read address is ADDRESS DYCSX MO...

Page 624: ...function is accomplished using the SYSCON registers Symbol a_b in the following figures refers to the highest order address line in the data bus Symbol a_m refers to the highest order address line of...

Page 625: ...ank interfaced to one 8 bit memory chip Fig 61 32 bit bank external memory interfaces bits MW 10 OE CS WE CE OE WE B3 B2 B1 B0 IO 31 0 A a_m 0 D 31 0 BLS 2 A a_b 2 BLS 3 BLS 0 BLS 1 a 16 bit wide memo...

Page 626: ...l rights reserved User manual Rev 2 1 10 December 2015 626 of 1441 NXP Semiconductors UM10503 Chapter 23 LPC43xx LPC43Sxx External Memory Controller EMC 23 8 6 3 8 bit wide memory bank connection Fig...

Page 627: ...l protocols Transfer protocol compatible with various vendors and devices The SPIFI memory is accessible by the DMA Software driver library available on the LPCware com website Supports execute in pla...

Page 628: ...ory Address SPIFI data 0x1400 0000 to 0x17FF FFFF Use this memory area for debugging code and for slightly improved performance 0x8000 0000 to 0x87FF FFFF Debug will not work if the program counter is...

Page 629: ...processor reading data in memory mode which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register This allows the flash memo...

Page 630: ...lect dual protocol 0 0 Quad protocol This protocol uses IO3 0 1 Dual protocol This protocol uses IO1 0 29 RFCLK Select active clock edge for input data 0 0 Rising edge Read data is sampled on rising e...

Page 631: ...d that is equal to DATALEN bit 3 When the test succeeds the SPIFI captures the byte that meets this test so that it can be read from the Data Register and terminates the command by raising CS The end...

Page 632: ...sing the byte value 0xA5 and cancelling this mode using 0xFF Many devices that require dummy delay bytes don t care about their contents in which case this register need not be written 23 21 FRAMEFORM...

Page 633: ...input data Load commands are waited if a command is in progress and the FIFO does not contain the number of bytes being loaded For Load Halfword and Load Word commands the least significant byte is re...

Page 634: ...he data Each such byte may require 8 or 2 SCK cycles depending on whether the intermediate field is in serial 2 bit or 4 bit format Intermediate bytes are output by the SPIFI and include post address...

Page 635: ...ata bits from the time that it drives CS LOW and drives the rest of the data on falling edges of SCK In mode 3 the SPIFI drives SCK LOW one half clock period after it drives CS LOW and drives data on...

Page 636: ...d data by setting the RFCLK bit When this bit is 1 the SPIFI samples data on the falling edge of the serial clock that follows the rising edge which is normally used RFCLK and FBCLK and MODE3 should n...

Page 637: ...he Command Register without writing the Memory Command Register thereafter the SPIFI responds with an Abort error After writing the Memory Command Register the contents of the flash would appear to th...

Page 638: ...er Thereafter If INTEN in the Control register is 1 the SPIFI will interrupt the processor when the erase or write operation and thus the Read Status command completes If not software can continually...

Page 639: ...User manual Rev 2 1 10 December 2015 639 of 1441 NXP Semiconductors UM10503 Chapter 24 LPC43xx LPC43Sxx SPI Flash Interface SPIFI DRQEN in the Control register is 1 MCINIT is 0 There are at least 4 b...

Page 640: ...e is selected To use the USB0 controller enable the PHY in the CREG0 register bit 5 The SOF VF indicator can be connected to Timer3 or the to SCT through the GIMA see Section 25 7 7 and Table 208 The...

Page 641: ...ed to connect several types of devices to each other in order to exchange data or for other purposes Many portable devices can benefit from the ability to communicate to each other over the USB interf...

Page 642: ...ions The Maximum Packet Size see Table 459 is dependent on the type of endpoint and the device configuration low speed full speed or high speed Table 457 USB related acronyms Acronym Description ATX A...

Page 643: ...Description USB0_IND0 O Port indicator LED control output USB0_IND1 O Port indicator LED control output USB0_PWR_FAULT I Port power fault signal indicating overcurrent condition this signal monitors...

Page 644: ...B0_VBUS disconnected ensures that OTG VBUS line pulsing does not go towards the cable 25 6 Register description USB0_VBUS I VBUS pin power on USB cable This pin includes an internal pull down resistor...

Page 645: ...0x0000 0186 Table 468 0x128 0x13C Reserved Device host operational registers USBCMD_D R W 0x140 USB command device mode 0x0008 0000 0 Table 469 USBCMD_H R W 0x140 USB command host mode 0x0008 0000 Tab...

Page 646: ..._D R W 0x184 Port 1 status control device mode 0 0x3C00 0004 Table 489 PORTSC1_H R W 0x184 Port 1 status control host mode 0 Table 490 0x188 0x1A0 OTGSC R W 0x1A4 OTG status and control 0 0x0020 0D09...

Page 647: ...ts of the PORTSC register Section 25 6 15 PTS parallel interface select STS serial transceiver select PTW parallel transceiver width PHCD PHY low power suspend WKOC WKDC WKCN wake signals PIC 1 0 port...

Page 648: ...composed into smaller unspecified length bursts 0x7 INCR16 non multiple transfers of INCR16 will be decomposed into smaller unspecified length bursts 31 3 Reserved Not used in device mode Writing a on...

Page 649: ...then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field The frame list must always be aligned on a 4K boundary...

Page 650: ...ng into high speed mode Software should use this bit to prevent an attach event before the device controller has been properly initialized 1 RST Controller reset Software uses this bit to reset the co...

Page 651: ...unrecognized R W 0 15 Not used in device mode 23 16 ITC Interrupt threshold control The system software uses this field to set the maximum rate at which the host device controller will issue interrupt...

Page 652: ...not process the periodic schedule 1 Use the PERIODICLISTBASE register to access the periodic schedule 5 ASE This bit controls whether the host controller skips processing the asynchronous schedule R W...

Page 653: ...See Table 471 0 23 16 ITC Interrupt threshold control The system software uses this field to set the maximum rate at which the host device controller will issue interrupts ITC contains the maximum int...

Page 654: ...n completion of a USB transaction results in an error condition this bit is set by the host device controller This bit is set along with the USBINT bit if the TD on which the error interrupt occurred...

Page 655: ...before connect this bit will be set at an interval of 1ms during the prelude to connect and chirp 8 SLI DCSuspend 0 R WC 0 The device controller clears the bit upon exiting from a Suspended state This...

Page 656: ...rt Resume bit is set as the result of a J K transition on the suspended port 3 FRI Frame list roll over 0 R WC 0 This bit is cleared by software writing a one to it 1 The Host Controller sets this bit...

Page 657: ...riodic schedule status is disabled 1 The periodic schedule status is enabled 15 AS Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule The Host Controlle...

Page 658: ...bit description continued Bit Symbol Value Description Reset value Access Table 474 USB Interrupt register in device mode USBINTR_D address 0x4000 6148 bit description Bit Symbol Description Reset val...

Page 659: ...USB Interrupt register in host mode USBINTR_H address 0x4000 6148 bit description Bit Symbol Description Access Reset value 0 UE USB interrupt enable When this bit is one and the USBINT bit in the USB...

Page 660: ...e and the SRI bit in the USBSTS register is one the host controller will issue an interrupt In host mode the SRI bit will be set every 125 s and can be used by the host controller as a time base The i...

Page 661: ...the SOF value 25 6 7 Device address DEVICEADDR device and Periodic List Base PERIODICLISTBASE host registers 25 6 7 1 Device mode The upper seven bits of this register represent the device address Af...

Page 662: ...vice Address register in device mode DEVICEADDR address 0x4000 6154 bit description Bit Symbol Value Description Reset value Access 23 0 Reserved 0 24 USBADRA Device address advance 0 Any write to USB...

Page 663: ...for the length of a burst of 32 bit words for RX and TX DMA data transfers is 16 words each Remark The value of the fields TXPBURST RXPBURST in register BURSTSIZE depends on the setting of the SBUSCF...

Page 664: ...e the end of the micro frame If so it proceeds to pre fill the TX FIFO If at anytime during the pre fill operation the time remaining the micro frame is Ts then the packet attempt ceases and the packe...

Page 665: ...em memory This value is ignored if the Stream Disable bit in USBMODE register is set 0x2 R W 12 8 TXSCHEATLTH Scheduler health counter This register increments when the host controller fails to fill t...

Page 666: ...his register enables the corresponding bit in the ENDPTNAK register Each Tx and Rx endpoint has a bit in the EPTNE and EPRNE field respectively Table 487 USB endpoint NAK register ENDPTNAK address 0x4...

Page 667: ...Bit 5 corresponds to endpoint 5 Bit 1 corresponds to endpoint 1 Bit 0 corresponds to endpoint 0 0x00 R W 15 6 Reserved 21 16 EPTNE Tx endpoint NAK Each bit enables the corresponding TX NAK bit If this...

Page 668: ...ort 1 Resume detected driven on port 7 SUSP Suspend In device mode this is a read only status bit 0 RO 0 Port not in Suspended state 1 Port in Suspended state 8 PR Port reset In device mode this is a...

Page 669: ...bit is always 0 in device mode 0 23 PHCD PHY low power suspend clock disable PLPSCD In device mode The PHY can be put into Low Power Suspend Clock Disable when the device is not running USBCMD Run St...

Page 670: ...1 Device is present on the port 1 CSC Connect status change Indicates a change has occurred in the port s Current Connect Status The host device controller sets this bit for all changes to the port de...

Page 671: ...bit to one to drive resume signaling The Host Controller sets this bit to one if a J to K transition is detected while the port is in the Suspended state When this bit transitions to a one because a J...

Page 672: ...delay in suspending a port if there is a transaction currently in progress on the USB 8 PR Port reset When software writes a one to this bit the bus reset sequence as defined in the USB Specification...

Page 673: ...s that the port is operating in test mode The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification Writing the PTC field to any of the FORCE_...

Page 674: ...tus of the PHY clock enabled 1 Writing a 1 disables the PHY clock Reading a 1 indicates the status of the PHY clock disabled 24 PFSC Port force full speed connect 0 R W 0 Port connects at any speed 1...

Page 675: ...o 1 when the OTG controller is in device mode This controls the pull down on USB_DM 0 R W 4 DP Data pulsing Setting this bit to 1 causes the pull up on USB_DP to be asserted for data pulsing during SR...

Page 676: ...the B session end threshold Software must write a 1 to this bit to clear it 0 R WC 21 ms1S 1 millisecond timer interrupt status This bit is set once every millisecond Software must write a 1 to this...

Page 677: ...alue Description Reset value Access 1 0 CM1_0 Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset This register can only be w...

Page 678: ...mode USBMODE_D address 0x4000 61A8 bit description continued Bit Symbol Value Description Reset value Access Table 494 USB Mode register in host mode USBMODE_H address 0x4000 61A8 bit description Bit...

Page 679: ...ow bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the...

Page 680: ...transfer descriptor to an endpoint Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer Hardware will clear this bit...

Page 681: ...s register indicates that a received transmit event occurred and software should read the corresponding endpoint queue to determine the transfer status If the corresponding IOC bit is set in the Trans...

Page 682: ...16 ETCE Endpoint transmit complete event for physical IN endpoints 5 to 0 This bit is set to 1 by hardware when a transmit event IN INTERRUPT occurred ETCE0 endpoint 0 ETCE5 endpoint 5 0 R WC 31 22 Re...

Page 683: ...Endpoint ok 1 Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host It will continue returning STALL until the bit is cleared by software...

Page 684: ...s between the host and device 0 WS 7 RXE Rx endpoint enable Remark An endpoint should be enabled only after it has been configured 0 R W 0 Endpoint disabled 1 Endpoint enabled 15 8 Reserved 16 TXS Tx...

Page 685: ...ust be a minimum of 133 ns 4 30 MHz clock cycles in duration to reset all logic correctly The ATX_RGEN module generates a reset signal towards the ATX fulfilling above 3 requirements no matter how the...

Page 686: ...Section 25 1 for connecting the SOF signal to other peripherals on the LPC43xx The USB OTG generates a SOF VF indicator signal which can be used by user specific external logic In FS mode the SOF VF...

Page 687: ...otified of the connect event and starts the reset Software will still receive notification of the connect event CCS bit in the PORTSC register but should not write the reset bit in the USBCMD register...

Page 688: ...ickly a few microseconds after connect will require at a minimum 50 ms this is the time for which the DCD must be ready to accept setup packets after having received notification that the reset has be...

Page 689: ...t reset operation and when the host and device negotiate a High Speed connection i e Chirp completes successfully Since this controller has an embedded Transaction Translator the port enable will alwa...

Page 690: ...ion Translator see USB 2 0 specification and for the EHCI controller moving packets between system memory and a USB HS hub Since the embedded Transaction Translator exists within the host controller t...

Page 691: ...11 17 3 Sequencing is provided a packet length estimator ensures no full speed low speed packet babbles into SOF time 2 USB 2 0 specification section 11 17 4 Transaction tracking for 2 data pipes 3 U...

Page 692: ...d addresses in the capability registers and operational register are used in device mode For read and write operations to these register note the following Always write zero to all EHCI reserved field...

Page 693: ...h will re assign the port owner for any device that does not connect at High Speed this host controller supports direct attach of non High Speed devices Therefore the following differences are importa...

Page 694: ...ure but must be aligned on 64 byte boundaries During priming of an endpoint the dTD device transfer descriptor is copied into the overlay area of the dQH see Figure 69 which starts at the nextTD point...

Page 695: ...modify this information while the corresponding endpoint is enabled Fig 69 Endpoint queue head data structure ENDPOINT CAPABILITIES CHARACTERISTICS BUFFER POINTER PAGE 0 BUFFER POINTER PAGE 1 BUFFER P...

Page 696: ...ocol where N is computed using Max_packet_length and the Total_bytes field in the dTD 01 Execute one transaction 10 Execute two transactions 11 Execute three transactions Remark Non isochronous endpoi...

Page 697: ...nsfer descriptor dTD The dTD describes to the device controller the location and quantity of data to be sent received for a given transfer The DCD should not attempt to modify any field in an active d...

Page 698: ...pointers can access Although it is possible to create a transfer up to 20 kB this assumes that the first offset into the first page is zero When the offset cannot be predetermined crossing past the f...

Page 699: ...field in the dTD 01 Execute one transaction 10 Execute two transactions 11 Execute three transactions Remark Non ISO and Non TX endpoints must set MultO 00 9 8 reserved R W 7 0 Status Status This fie...

Page 700: ...minimum it is necessary to have the queue heads setup for endpoint zero before the device attach occurs Shortly after the device is enabled a USB reset will occur followed by a setup packet arriving a...

Page 701: ...ters the Powered state A transition from the Powered state to the Attached state occurs when the Run Stop bit is set to a 1 After receiving a reset on the bus the port will enter the defaultFS or defa...

Page 702: ...upt Enable is set After a reset is received all endpoints except endpoint 0 are disabled and any primed transactions will be cancelled by the device controller The concept of priming will be clarified...

Page 703: ...uspend mode when there is bus activity A USB device may also request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake up The ability of a device...

Page 704: ...ior in each direction For example the DCD can configure endpoint 1 IN to be a bulk endpoint and endpoint 1 OUT to be an isochronous endpoint This helps to conserve the total number of endpoints requir...

Page 705: ...y cleared by the device controller at the start of a new control transaction setup phase When enabling a protocol stall the DCD should enable the stall bits both directions as a pair A single write to...

Page 706: ...ime stated in the USB 2 0 Specification At USB 1 1 Full or Low Speed rates this turnaround time was significant and the USB 1 1 device controllers were designed so that the device controller could acc...

Page 707: ...nts is identical to priming of transmit endpoints from the point of view of the DCD At the device controller the major difference in the operational model is that there is no data movement of the lead...

Page 708: ...the successful completion of the packets described by the dTD the active bit in the dTD will be cleared and the next pointer will be followed when the Terminate bit is clear When the Terminate bit is...

Page 709: ...g an interrupt and inspecting USBMODE to determine that a setup packet was received on a particular pipe 1 Duplicate contents of dQH SetupBuffer into local software byte array 2 Write 1 to clear corre...

Page 710: ...ving a new setup packet the status and or handshake phases may still be pending from a previous control sequence These should be flushed deallocated before linking a new status and or handshake dTD fo...

Page 711: ...orrectly sized and the DCD is responsive 25 10 9 Isochronous endpoint operational model Isochronous endpoints are used for real time scheduled delivery of data and their operational model is significa...

Page 712: ...bit set in the status field indicates a fulfillment error condition When a fulfillment error occurs the device controller will force retire the ISO dTD and move to the next ISO dTD It is important to...

Page 713: ...ccur at a specific micro frame number N the DCD should interrupt on SOF during frame N 1 When the FRINDEX N 1 the DCD must write the prime bit The device controller will prime the isochronous endpoint...

Page 714: ...inters and the dTD overlay examined in section Section 25 10 6 the dQH also contains the following parameters for the associated endpoint Multiplier Maximum Packet Length Interrupt On Setup The comple...

Page 715: ...cknowledge has occurred the DCD must not attempt to access the setup buffer in the dQH RX Only the local software copy should be examined 3 Check for pending data or status dTD s from previous control...

Page 716: ...active bit set to 1 and all remaining status bits set to 0 6 Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer 7 Initialize buffer pointer page 1 through p...

Page 717: ...if the Interrupt On Complete bit was set or alternately the DCD can poll the endpoint complete register to find when the dTD had been executed After a dTD has been executed DCD can check the status bi...

Page 718: ...h using ENDPTFLUSH A safeguard is in place to refuse the flush to ensure that the packet in progress completes successfully The DCD may need to repeatedly flush any endpoints that fail to flush by rep...

Page 719: ...terrupts Error interrupts will be least frequent and should be placed last in the interrupt service routine Table 518 High frequency interrupt events Execution order Interrupt Action 1a USB interrupt...

Page 720: ...buffer pointer in endpoint transfer descriptors or in endpoint queue head got corrupted pointing to inaccessible memory location The DCD should always provide pointers to the USB controller accessibl...

Page 721: ...y suspending the clock The implementation of low power states in the USB HS core is dependent on the use of the device role host or peripheral whether the device is bus powered and the selected clock...

Page 722: ...de as a result of a suspend command from the host Suspend is signaled on the bus by 3 ms of idle time on the bus This will generate a suspend interrupt to the software at which point the software must...

Page 723: ...detect a true suspend command issued by host 25 12 3 Host power states From an operational state when a host gets a low power request it must set the suspend bit in the port controller This will put...

Page 724: ...ent router see Table 83 Software should check for this signal to be HIGH before stopping the USB PLL and putting the chip in low power mode Note that the event router block doesn t support a raw pin s...

Page 725: ...ice OTG controller a change on vbusvalid occurs VBUS threshold at 4 4 V is crossed a change on bvalid occurs VBUS threshold at 4 0 V is crossed The vbusvalid and bvalid signals coming from the transce...

Page 726: ...frame length adjustment in USB host mode are located in the CREG block see Table 113 parts with on chip flash only 26 2 1 Full speed mode without external PHY In Full speed mode use CLK_USB1 to genera...

Page 727: ...gnal with an external clock see Section 25 7 7 1 26 4 General description The USB1 controller provides plug and play connection of peripheral devices to a host with three different data speeds High Sp...

Page 728: ...l up This pull up is enabled when software sets the RS bit Bit 0 in the USBCMD register The USB1 controller checks whether the USB1_VBUS pin is pulled HIGH there is no voltage monitoring For applicati...

Page 729: ...522 USB1 pin description Pin function Direction Description Table 523 Register access abbreviations Abbreviation Description R W Read Write R WC Read Write one to Clear R WO Read Write Once RO Read O...

Page 730: ...000 Table 547 BINTERVAL R W 0x174 Length of virtual frame 0x0000 0000 Table 548 ENDPTNAK R W 0x178 Endpoint NAK device mode 0x0000 0000 Table 549 ENDPTNAKEN R W 0x17C Endpoint NAK Enable device mode 0...

Page 731: ...downstream ports implemented on this host controller 0x1 RO 4 PPC Port Power Control This field indicates whether the host controller implementation includes port power control 0x1 RO 7 5 These bits a...

Page 732: ...r high speed queue heads in the Asynchronous Schedule The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule P...

Page 733: ...tached state is not recommended since the effect on an attached host is undefined In order to ensure that the device is not in an attached state before initiating a device controller reset all primed...

Page 734: ...shed the transaction and has entered the stopped state Software should not write a one to this field unless the host controller is in the Halted state i e HCHalted in the USBSTS register is a one 1 Wh...

Page 735: ...ng the doorbell When the host controller has evicted all appropriate cached schedule states it sets the Interrupt on Async Advance status bit in the USBSTS register If the Interrupt on Sync Advance En...

Page 736: ...ield to set the maximum rate at which the host device controller will issue interrupts ITC contains the maximum interrupt interval measured in micro frames Valid values are shown below All other value...

Page 737: ...n completion of a USB transaction results in an error condition this bit is set by the Host Device Controller This bit is set along with the USBINT bit if the TD on which the error interrupt occurred...

Page 738: ...ore connect this bit will be set at an interval of 1ms during the prelude to connect and chirp 8 SLI DCSuspend 0 R WC 0 The device controller clears the bit upon exiting from a Suspended state This bi...

Page 739: ...t Resume bit is set as the result of a J K transition on the suspended port 3 FRI Frame list roll over 0 R WC 0 This bit is cleared by software writing a one to it 1 The Host Controller sets this bit...

Page 740: ...riodic schedule status is disabled 1 The periodic schedule status is enabled 15 AS Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule The Host Controlle...

Page 741: ...r bit description continued Bit Symbol Value Description Reset value Access Table 535 USB Interrupt register in device mode USBINTR_D address 0x4000 7148 bit description Bit Symbol Description Reset v...

Page 742: ...36 USB Interrupt register in host mode USBINTR_H address 0x4000 7148 bit description Bit Symbol Description Access Reset value 0 UE USB interrupt enable When this bit is one and the USBINT bit in the...

Page 743: ...s one and the SRI bit in the USBSTS register is one the host controller will issue an interrupt In host mode the SRI bit will be set every 125 s and can be used by the host controller as a time base T...

Page 744: ...6 6 6 Device address DEVICEADDR and Periodic List Base PERIODICLISTBASE registers 26 6 6 1 Device mode The upper seven bits of this register represent the device address After any controller reset or...

Page 745: ...R address 0x4000 7154 bit description Bit Symbol Value Description Reset value Access 23 0 reserved 0 24 USBADRA Device address advance 0 Any write to USBADR are instantaneous 1 When the user writes a...

Page 746: ...USB DMA controller Writes must be in Dwords The default for the length of a burst of 32 bit words for RX and TX DMA data transfers is 16 words each Table 542 USB Endpoint List Address register in devi...

Page 747: ...e end of the micro frame If so it proceeds to pre fill the TX FIFO If at anytime during the pre fill operation the time remaining the micro frame is Ts then the packet attempt ceases and the packet is...

Page 748: ...x4000 7164 bit description Bit Symbol Description Reset value Access 7 0 TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mo...

Page 749: ...ress 0x4000 7170 bit description Bit Symbol Value Description Access Reset value 7 0 ULPIDATWR When a write operation is commanded the data to be sent is written to this field R W 0 15 8 ULPIDATRD Aft...

Page 750: ...Host mode This register is not used in host mode Table 548 USB BINTERVAL register BINTERVAL address 0x4000 7174 bit description in device host mode Bit Symbol Description Reset value Access 3 0 BINT b...

Page 751: ...atus port reset suspend and current connect status It is also used to initiate test mode or force signaling This register allows software to put the PHY into low power Suspend mode and disable the PHY...

Page 752: ...ed 0 RO 5 4 Reserved 0 RO 6 FPR Force port resume After the device has been in Suspended state for 5 ms or more software must set this bit to one to drive resume signaling before clearing The Device C...

Page 753: ...E_FS 20 Not used in device mode This bit is always 0 in device mode 0 21 Not used in device mode This bit is always 0 in device mode 0 22 Not used in device mode This bit is always 0 in device mode 0...

Page 754: ...mode PORTSC1_D address 0x4000 7184 bit description Bit Symbol Value Description Reset value Access Table 552 Port Status and Control register in host mode PORTSC1_H address 0x4000 7184 bit descriptio...

Page 755: ...does not have an over current condition 1 The port has currently an over current condition 5 OCC Over current change This bit gets set to one when there is a change to Over current Active Software cle...

Page 756: ...ended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB 8 PR Port reset When software writes a one to this bit the bus reset sequence as def...

Page 757: ...cators are off 0x1 Amber 0x2 Green 0x3 Undefined 19 16 PTC3_0 Port test control Any value other than 0000 indicates that the port is operating in test mode The FORCE_ENABLE_FS and FORCE ENABLE_LS are...

Page 758: ...bles the PHY clock Reading a 0 indicates the status of the PHY clock enabled 1 Writing a 1 disables the PHY clock Reading a 1 indicates the status of the PHY clock disabled 24 PFSC Port force full spe...

Page 759: ...rating mode after reset This register can only be written once after reset If it is necessary to switch modes software must reset the controller by writing to the RESET bit in the USBCMD register befo...

Page 760: ...USBMODE_D address 0x4000 71A8 bit description continued Bit Symbol Value Description Reset value Access Table 555 USB Mode register in host mode USBMODE_H address 0x4000 71A8 bit description Bit Symb...

Page 761: ...r low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the...

Page 762: ...w transfer descriptor to an endpoint Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer Hardware will clear this b...

Page 763: ...n this register indicates that a received transmit event occurred and software should read the corresponding endpoint queue to determine the transfer status If the corresponding IOC bit is set in the...

Page 764: ...ETCE Endpoint transmit complete event for physical IN endpoints This bit is set to 1 by hardware when a transmit event IN INTERRUPT occurred ETCE0 endpoint 0 ETCE3 endpoint 3 0 R WC 31 20 Reserved Tab...

Page 765: ...oint ok 1 Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host It will continue returning STALL until the bit is cleared by software or i...

Page 766: ...between the host and device 0 WS 7 RXE Rx endpoint enable Remark An endpoint should be enabled only after it has been configured 0 R W 0 Endpoint disabled 1 Endpoint enabled 15 8 Reserved 16 TXS Tx en...

Page 767: ...utput signal For USB1 this signal is not connected to any register The SUSP_CTRL module also generates an output signal indicating whether the AHB clock is needed or not If not the AHB clock is allowe...

Page 768: ...ns software clears the PORTSC1 PHCD bit a device is connected and the PORTSC1 WKCN bit is set a device is disconnected an the PORTSC1 WKDC bit is set an over current condition occurs and the PORTSC1 W...

Page 769: ...ng only the required interface needed to interface with Devices using the USB CDC ACM Class Communication Device Class function driver initialization parameter data structure Table 589 USBD_CDC_API cl...

Page 770: ...SBD_HID_INIT_PARAM class structure HID class API functions structure This structure contains pointers to all the functions exposed by the HID function driver module Table 596 USBD_HW_API class structu...

Page 771: ...structure Ptr to USB ROM Driver table Ptr to Device Table 2 Reserved Ptr to Device Table 1 Ptr to USB ROM Driver table hw core dfu Ptr to Function 2 Ptr to Function 0 Ptr to Function 1 Ptr to Functio...

Page 772: ...OL_MANAGEMENT_DESCRIPTOR bDescriptorType bDescriptorSubtype uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR bDescriptorSubtype bmCapabilities uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR bm...

Page 773: ...DC_LINE_CODING bDataBits Table 569 _CDC_UNION_1SLAVE_DESCRIPTOR class structure Member Description sUnion CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR sUnion bSlaveInterfaces...

Page 774: ...t POST_PACK _HID_DESCRIPTOR _HID_DESCRIPTOR_LISTPRE_PACK struct POST_PACK _HID_DESCRIPTOR _HID_DESCRIPTOR_LIST _HID_DESCRIPTOR DescriptorList 1 1 Array of one or more descriptors Table 573 _HID_DESCRI...

Page 775: ...Flags uint8_t _MSC_CBW bmFlags bLUN uint8_t _MSC_CBW bLUN bCBLength uint8_t _MSC_CBW bCBLength CB uint8_t _MSC_CBW CB 16 16 Table 576 _MSC_CSW class structure Member Description dSignature uint32_t _M...

Page 776: ..._desc device_qualifier uint8_t _USB_CORE_DESCS_T device_qualifier Pointer to USB device qualifier descriptor For full speed only implementation this pointer should be set to null 0 Table 580 _USB_DEVI...

Page 777: ...s bDescriptorType uint8_t _USB_INTERFACE_DESCRIPTOR bDescriptorType INTERFACE Descriptor Type bInterfaceNumber uint8_t _USB_INTERFACE_DESCRIPTOR bInterfaceNumber Number of this interface Zero based va...

Page 778: ...uint8_t _USB_OTHER_SPEED_CONFIGURATION IConfiguration Index of string descriptor bmAttributes uint8_t _USB_OTHER_SPEED_CONFIGURATION bmAttributes Same as Configuration descriptor bMaxPower uint8_t _U...

Page 779: ...G Descriptor Type bString uint16_t _USB_STRING_DESCRIPTOR bString UNICODE encoded string Table 586 _WB_T class structure Member Description L uint8_t _WB_T L lower byte H uint8_t _WB_T H upper byte Ta...

Page 780: ...ry location from where the stack can allocate data and buffers Remark The memory address set in this field should be accessible by USB DMA controller Also this value should be aligned on 2048 byte bou...

Page 781: ...ually enabled and disabled via the USB interrupt register USB_WakeUpCfg USB_PARAM_CB_T USBD_API_INIT_PARAM USB_WakeUpCfg Event for remote wake up configuration when enabled This event fires when the U...

Page 782: ...device from enumerating correctly or operate properly USB_Feature_Event USB_CB_T USBD_API_INIT_PARAM USB_Feature_Event Event for USB feature changed This event fires when a the USB host send set clea...

Page 783: ...ndNotification USBD_HANDLE_T hCdc uint8_t bNotification uint16_t data Function to send CDC class notifications to host This function is called by application layer to send CDC class notifications to h...

Page 784: ...function is provided by the application software This function gets called when host sends CIC management element get requests Remark Applications implementing Abstract Control Model subclass can set...

Page 785: ...pBuffer pointer the stack will send STALL condition to host 2 Second when the data is received from the host This time the length param is set with number of data bytes received Parameters 1 hCdc Han...

Page 786: ...s Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next...

Page 787: ...urns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other e...

Page 788: ...oftware This function gets called when host sends a GET_ENCAPSULATED_RESPONSE request Parameters 1 hCdc Handle to CDC function driver 2 feature Communication feature type 3 buffer Pointer to a pointer...

Page 789: ...ed by the application software This function gets called when host sends a CLEAR_COMM_FEATURE request In the call back the application should Clears the settings for a particular communication feature...

Page 790: ...de_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditi...

Page 791: ...ess or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions CDC_InterruptEP_Hdlr E...

Page 792: ...xxx For other error conditions Table 590 USBD_CDC_INIT_PARAM class structure Member Description Table 591 USBD_CORE_API class structure Member Description RegisterClassHandler ErrorCode_t ErrorCode_t...

Page 793: ...int handlers SetupStage void void USBD_CORE_API SetupStage USBD_HANDLE_T hUsb Function to set EP0 state machine in setup state This function is called by USB stack and the application layer to set the...

Page 794: ...ion layer to set the EP0 state machine in status_in state This function will send zero length IN packet on EP0 to host indicating positive status Remark This interface is provided to users to invoke t...

Page 795: ...tate machine in stall state This function is called by USB stack and the application layer to generate STALL signalling on EP0 endpoint This function will also reset the EP0Data buffer Remark This int...

Page 796: ...led by application layer to initialize DFU function driver module Parameters 1 hUsb Handle to the USB device stack 2 param Structure containing DFU function driver module initialization parameters Ret...

Page 797: ...is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 3 bwPollTimeout Pointer to a 3 byte buffer which the callback implementer should fill wi...

Page 798: ...o issue reset instead the device has to do it automatically by disconnect and connect procedure hUsbHandle DFU control structure Parameters 1 hUsb Handle DFU control structure Returns Nothing DFU_Ep0_...

Page 799: ...initialization parameters Returns Returns the required memory size in bytes init ErrorCode_t ErrorCode_t USBD_HID_API init USBD_HANDLE_T hUsb USBD_HID_INIT_PARAM_T param Function to initialize HID fu...

Page 800: ...T_PARAM report_data Pointer to an array of HID report descriptor data structure Remark This array should be of global scope HID_GetReport ErrorCode_t USBD_HID_INIT_PARAM HID_GetReport USBD_HANDLE_T hH...

Page 801: ...on software could provide this callback HID_GetPhysDesc handler to handle get physical descriptor requests sent by the host When host requests Physical Descriptor set 0 application should return a spe...

Page 802: ...hould returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx Fo...

Page 803: ...er Application which send reports to host on interrupt endpoint should provide an endpoint event handler through this data member This data member is ignored if the interface descriptor Parameters 1 h...

Page 804: ...hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions HID_GetReportDesc ErrorCode_t USBD_HID_INIT_PARAM HID_GetReportDesc USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pB...

Page 805: ...ride the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure Application which like the default handler should set this da...

Page 806: ...layers On successful initialization the function returns a handle to USB device stack which should be passed to the rest of the functions Parameters 1 phUsb Pointer to the USB device stack handle of t...

Page 807: ...the USB device stack Returns Nothing Reset void void USBD_HW_API Reset USBD_HANDLE_T hUsb Function to Reset USB device stack and hardware controller Reset USB device stack and hardware controller Disa...

Page 808: ...n to set USB address assigned by host in device controller hardware This function is called automatically when USB_REQUEST_SET_ADDRESS request is received by the stack from USB host This interface is...

Page 809: ...sers who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the USB device stack 2 pEPD Endpoint descriptor...

Page 810: ...ram to 0x0 3 event Type of endpoint event See USBD_EVENT_T for more details 4 enable 1 enable event 0 disable event Returns Returns ErrorCode_t type to indicate success or error condition Return value...

Page 811: ...um Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Returns Nothing SetTestMode ErrorCode_t ErrorCode_t USBD_HW_API SetTestMode USBD_HANDLE_T hUsb uint8_t mode Funct...

Page 812: ...he specified endpoint This function is called by USB stack and the application layer to queue a read request on the specified endpoint Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint...

Page 813: ...1_IN is represented by 0x81 number 3 pData Pointer to the data buffer from where data is to be copied 4 cnt Number of bytes to write Returns Returns the number of bytes written WakeUp void void USBD_H...

Page 814: ...ark Some memory areas are not accessible by all bus masters Parameters 1 param Structure containing MSC function driver module initialization parameters Returns Returns the required memory size in byt...

Page 815: ...nt in response to the SCSI Inquiry command Remark The data pointed by the pointer should be of global scope BlockCount uint32_t USBD_MSC_INIT_PARAM BlockCount Number of blocks present in the mass stor...

Page 816: ...drivers implemented in stack are written with zero copy model Meaning the stack doesn t make an extra copy of buffer before writing reading data from USB hardware FIFO Hence the parameter is pointer...

Page 817: ...sent by the host 3 length Number of bytes to verify Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK If data in the buffer matches the data at destination...

Page 818: ...ler function address as this data member of the parameter structure Application which like the default handler should set this data member to zero before calling the USBD_MSC_API Init Remark Parameter...

Page 819: ...I in the CREG6 register in the CREG block see Table 105 28 3 Features 10 100 Mbit s DMA support IEEE 1588 Time stamping block IEEE 1588 advanced Time stamp support IEEE 1588 2008 v2 Power management r...

Page 820: ...ssion and reception with Scatter Gather DMA off loads many operations from the CPU Additional features such as IEEE 1588 Time Stamping IEEE 1588 2002 and IEEE Advanced Time Stamp support IEEE 1588 200...

Page 821: ...T_MDC O Ethernet MIIM Clock RMII interface ENET_RXD 1 0 I Ethernet Receive Data ENET_TXD 1 0 O Ethernet Transmit Data ENET_RX_DV I Ethernet Receive Data Valid ENET_REF_CLK I Ethernet Reference Clock E...

Page 822: ...MT control and status 0x0000 0000 Table 613 0x0030 0x0034 Reserved MAC_INTR RO 0x0038 Interrupt status register 0x0000 0000 Table 614 MAC_INTR_MASK R W 0x003C Interrupt mask register 0x0000 0000 Table...

Page 823: ...eserved DMA_CURHOST_TRANS_DES RO 0x1048 Current host transmit descriptor register 0x0000 0000 Table 641 DMA_CURHOST_REC_DES RO 0x104C Current host receive descriptor register 0x0000 0000 Table 642 DMA...

Page 824: ...6 bit times for 1000 Mbps and 512 bit times for 10 100 Mbps the MAC waits before rescheduling a transmission attempt during retries after a collision This bit is applicable only to Half Duplex mode an...

Page 825: ...100 Mbps 0 15 PS Port select 1 MII 100 Mbp this is the only allowed value 1 RO 16 DCRS Disable carrier sense during transmission When set high this bit makes the MAC transmitter ignore the MII CRS si...

Page 826: ...allows no more than 2 048 bytes 10 240 if JE is set high of the frame being received and cuts off any bytes received after that 0 R W 31 24 Reserved 0x00 RO Table 602 MAC Configuration register MAC_CO...

Page 827: ...0 R W 5 DBF Disable Broadcast Frames When this bit is set the AFM module filters all incoming broadcast frames When this bit is reset the AFM module passes all received broadcast frames 0 R W 7 6 PCF...

Page 828: ...ly after at least 4 clock cycles in the destination clock domain when double synchronization is enabled The Hash Table High register contains the higher 32 bits of the Hash table See Section 28 7 1 fo...

Page 829: ...e a Write operation using the MII Data register If this bit is not set this will be a Read operation placing the data in the MII Data register 0 R W 5 2 CR CSR clock range The CSR Clock Range selectio...

Page 830: ...Control block to generate a Pause Control frame The fields of the control frame are selected as specified in the 802 3x specification and the Pause Time value from this register is used in the Pause...

Page 831: ...oller input signal for the backpressure function When the MAC is configured to Full Duplex mode the BPA is automatically disabled 0 R W 1 TFE Transmit Flow Control Enable In Full Duplex mode when this...

Page 832: ...RO 31 16 PT Pause time This field holds the value to be used in the Pause Time field in the transmit control frame If the Pause Time bits is configured to be double synchronized to the MII clock doma...

Page 833: ...xFIFO fill level below flow control de activate threshold 10 RxFIFO fill level above flow control activate threshold 11 RxFIFO Full 0 RO 15 10 Reserved RO 16 TXIDLESTAT When high it indicates that the...

Page 834: ...2C bit description Bit Symbol Description Reset value Access 0 PD Power down This register field can be read by the application Read can be set to 1 by the application with a register write of 1 Write...

Page 835: ...tion to be a wake up frame 0 R W 30 10 Reserved 0x00 0000 RO 31 WFFRPR Wake up Frame Filter Register Pointer Reset This register field can be read by the application Read can be set to 1 by the applic...

Page 836: ...or exceeds the value specified in the Target Time High and Low registers There is an overflow in the seconds register This bit is cleared on reading the byte 0 of the Timestamp Status register Table...

Page 837: ...e station 28 6 16 MAC IEEE1588 time stamp control register This register controls the operation of the System Time generator and the snooping of PTP packets for time stamping in the Receiver Table 616...

Page 838: ...red to 0 by the Ethernet core Self Clear When set the system time is updated added subtracted with the value specified in the Time stamp High Update and Time stamp Low Update registers This register b...

Page 839: ...snapshot is taken for all other messages except Announce Management and Signaling 0 R W 15 TSMSTRENA Enable Snapshot for Messages Relevant to Master When set the snapshot is taken for messages relevan...

Page 840: ...it is updated on a continuous basis there is some delay from the actual time due to clock domain transfer latencies 28 6 19 System time nanoseconds register This register contains 32 bits of the nano...

Page 841: ...Time value Table 622 System time nanoseconds register NANOSECONDS address 0x4001 070C bit description Bit Symbol Description Reset value Access 30 0 TSSS Time stamp sub seconds The value in this field...

Page 842: ...hese registers Table 624 System time nanoseconds update register NANOSECONDSUPDATE address 0x4001 0714 bit description Bit Symbol Description Reset value Access 30 0 TSSS Time stamp sub seconds The va...

Page 843: ...and is automatically cleared to 0 on a register read A register write of 0 has no effect on this field Table 627 Target time nanoseconds register TARGETNANOSECONDS address 0x4001 0720 bit description...

Page 844: ...not clear this type of field and a register write of 0 to this bit has no effect on this field When this bit is set the MAC DMA Controller resets all MAC Subsystem internal registers and logic It is c...

Page 845: ...over TxDMA requests in the following ratio This is valid only when the DA bit is reset 00 1 to 1 01 2 to 1 10 3 to 1 11 4 to 1 00 R W 16 FB Fixed burst This bit controls whether the AHB Master interfa...

Page 846: ...erface will start all bursts of length more than 16 with INCR undefined burst whereas it will revert to fixed burst transfers INCRx and SINGLE for burst length of 16 and below 0 R W 27 TXPR When set t...

Page 847: ...in the host s physical memory space and must be Word aligned The DMA internally converts it to bus width aligned address by making the corresponding LSB to low Writing to this register is permitted on...

Page 848: ...ad Only 0 R W Table 636 DMA Status register DMA_STAT address 0x4001 1014 bit description Bit Symbol Description Reset value Access 0 TI Transmit interrupt This bit indicates that frame transmission is...

Page 849: ...TL Transmit FIFO 0 R W 12 11 Reserved 0 RO 13 FBI Fatal bus error interrupt This bit indicates that a bus error occurred as detailed in bits 25 23 When this bit is set the corresponding DMA engine dis...

Page 850: ...Descriptor 010 Reserved 011 Running Waiting for receive packet 100 Suspended Receive Descriptor Unavailable 101 Running Closing Receive Descriptor 110 TIME_STAMP write state 111 Running Transferring...

Page 851: ...MODE address 0x4001 1018 bit description Bit Symbol Description Reset value Access 0 Reserved 0 RO 1 SR Start stop receive When this bit is set the Receive process is placed in the Running state The D...

Page 852: ...current position in the list which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously If the current descri...

Page 853: ...letes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host In order to complete this flush operation the PHY transmit c...

Page 854: ...eive Buffer Unavailable Interrupt is enabled When this bit is reset the Receive Buffer Unavailable Interrupt is disabled 0 R W 8 RSE Received stopped enable When this bit is set with Abnormal Interrup...

Page 855: ...w DMA_STAT register bit 5 Transmit underflow DMA_STAT register bit 7 Receiver buffer unavailable DMA_STAT register bit 8 Receive process stopped DMA_STAT register bit 9 Receive watchdog timeout DMA_ST...

Page 856: ...matically cleared to 0 on a register read A register write of 0 has no effect on this field Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable Thi...

Page 857: ...e Access 7 0 RIWT RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set The watchdog timer gets triggered with the programmed value afte...

Page 858: ...set in the selected register 4 In the MAC_FRAME_REGISTER enable the HMC bit bit 2 for multicast hash filtering or the HUC bit bit 1 for unicast hash filtering 28 7 1 1 Example for a unicast MAC addre...

Page 859: ...ote wake up frame enable and Magic Packet enable These enables are in the PMT Control and Status register and are programmed by the Application When the power down mode is enabled in the PMT then all...

Page 860: ...from which filter i examines the frames This 8 bit pattern offset is the offset for the filter i first byte to be examined The minimum allowed is 12 which refers to the 13th byte of the frame The offs...

Page 861: ...essed to the node on the network Only Magic Packets that are addressed to the device or a broadcast address will be checked to determine whether they meet the wake up requirements Magic Packets that p...

Page 862: ...er Down mode by appropriately configuring the PMT registers 5 Enable the MAC Receiver and enter Power Down mode 6 Gate the application and transmit clock inputs to the core and other relevant clocks i...

Page 863: ...e clocks of varying inherent precision resolution and stability to synchronize The protocol supports system wide synchronization accuracy in the sub microsecond range with minimal network and local cl...

Page 864: ...must be captured for Ethernet ports at MII 2 The slave receives the Sync message and also captures the exact time t2 using its timing reference 3 The master sends a Follow_up message to the slave whi...

Page 865: ...his module and updated using the input reference clock This time is the source for taking snapshots timestamps of Ethernet frames being transmitted or received at the MII The System Time counter can b...

Page 866: ...drifts lower to 65 MHz for example the ratio is 65 50 or 1 3 and the value to set in the addend register is 232 1 30 or 0xC4EC4EC4 If the clock drifts higher to 67 MHz for example the addend register...

Page 867: ...n is given by ClockDiffCountn MasterClockCountn SlaveClockCountn The frequency scaling factor for slave clock FreqScaleFactorn is given by FreqScaleFactorn MasterClockCountn ClockDiffCountn SlaveClock...

Page 868: ...tamping the DMA does not alter RDES6 or RDES7 28 7 4 5 Timestamp error margin According to the IEEE 1588 specifications a timestamp must be captured at the SFD of the transmitted and received frames a...

Page 869: ...type frames Provides an option to take snapshot of only event messages Provides an option to take the snapshot based on the clock type ordinary boundary end to end and peer to peer Provides an option...

Page 870: ...een the two ports Port 2 returns the Pdelay_Resp message as quickly as possible after the receipt of the Pdelay_Req message The Port 2 returns any one of the following The difference between the times...

Page 871: ...ollowing PTP message types version 1 or version 2 You cannot take the snapshots for both PTP message types You can take the snapshot by setting the control bit TSVER2ENA and selecting the snapshot mod...

Page 872: ...for taking snapshot for the event messages related to Pdelay is added The transparent clock corrects only the SYNC and Follow up message As discussed earlier this can be achieved using the message st...

Page 873: ...tions for the tagged frames are offset by 4 This is based on Annex D of IEEE 1588 2008 standard and the message format defined in Table 648 sequenceId 2 30 controlField 1 1 32 logMessageInterva 1 33 T...

Page 874: ...Delay_Resp 0x04 Management PTP Message Type Field IEEE version 2 42 nibble 0x0 0x1 0x2 0x3 0x8 0x9 0xB 0xC 0xD 0x0 SYNC 0x1 Delay_Req 0x2 Pdelay_Req 0x3 Pdelay_Resp 0x8 Follow_Up 0x9 Delay_Resp 0xA P...

Page 875: ...sp 0x8 Follow_Up 0x9 Delay_Resp 0xA Pdelay_Resp_Follow_Up 0xB Announce 0xC Signaling 0xD Management PTP Version 75 nibble 0x1 or 0x2 0x1 Supports PTP version 1 0x2 Supports PTP version 2 Table 652 IPv...

Page 876: ...noseconds field is the fractional portion of the timestamp in units of nanoseconds For example 2 000000001 nanoseconds are represented as nanoSeconds 0x0000_0001 The nanoseconds field supports the fol...

Page 877: ...e ethernet controller also supports PTP messages over VLAN frames The MAC provides the time stamp along with EOF An additional signal validates the presence of timestamp for the receive frame The MTL...

Page 878: ...ne for transmission The base address of each list is written into DMA Registers Table 634 and Table 635 A descriptor list is forward linked either implicitly or explicitly The last descriptor may poin...

Page 879: ...the DMA with the starting address of each list 4 Write to MAC Registers Table 603 Table 605 and Table 604 for desired filtering options 5 Write to MAC Register Table 602 to configure the operating mo...

Page 880: ...han the configured burst length is detected in the Receive FIFO The DMA indicates the start address and the number of transfers required to the AHB Master Interface When the AHB Interface is configure...

Page 881: ...width If a descriptor is marked as last then the buffer may not be full as indicated by the buffer size in RDES1 To compute the amount of valid data in this final buffer the driver must read the fram...

Page 882: ...Data Buffer address from the acquired descriptor 5 The DMA fetches the Transmit data from the Host memory and transfers the data to the MTL for transmission 6 If an Ethernet frame is stored over data...

Page 883: ...the Status descriptor of the first if the OSF bit is set in DMA Operation mode register bit 2 As the transmit process finishes transferring the first frame it Fig 85 TxDMA operation in default mode S...

Page 884: ...frame transmission status and Time stamp Once the status is available the DMA writes the Time stamp to TDES2 and TDES3 if such Time stamp was captured as indicated by a status bit The DMA then writes...

Page 885: ...e status word to prev frame s TDES0 Transfer data from buffer s AHB error Own bit set AHB error Frame xfer complete Time stamp present AHB error Write time stamp to TDES2 TDES3 for previous frame AHB...

Page 886: ...t on Completion TDES1 31 was set Transmit Interrupt DMA Status register bit 0 is set the Next Descriptor is fetched and the process repeats The actual frame transmission begins after the MTL Transmit...

Page 887: ...nsferred the DMA sets the Descriptor Error bit in the RDES0 unless flushing is disabled The DMA closes the current descriptor clears the Own bit and marks it as intermediate by clearing the Last Segme...

Page 888: ...eration Re Fetch next descriptor AHB error No Own bit set Yes Yes Stop RxDMA Start RxDMA Start AHB error No RxDMA suspended Yes Frame data available Wait for frame data Write data to buffer s Yes Yes...

Page 889: ...e FIFO in Store and Forward mode If the frame fails the address filtering it is dropped in the MAC block itself unless Receive All bit 31 is set in the MAC Frame Filter register Table 603 Frames that...

Page 890: ...t in DMA Interrupt Enable Register Table 638 Interrupts are not queued and if the interrupt event occurs before the driver has responded to it no additional interrupts are generated For example the Re...

Page 891: ...s 8 DWORDS of memory for every descriptor When Timestamping or Receive IPC FullOffload engine are not enabled the extended descriptors are not required and the SW can use alternate descriptors with th...

Page 892: ...89 When Advanced timestamp feature support is enabled TDES0 has additional control bits 6 3 for channel 1 and channel 2 For channel 0 the bits 6 3 are ignored The bits 6 3 are described in Table 654 F...

Page 893: ...sion process enters the Suspended state and sets both Transmit Underflow Register 5 5 and Transmit Interrupt Register 5 0 2 ED Excessive Deferral When set this bit indicates that the transmission has...

Page 894: ...on and issues an error status in case of a mismatch 13 FF Frame Flushed When set this bit indicates that the DMA MTL flushed the frame due to a software Flush command given by the CPU 14 JT Jabber Tim...

Page 895: ...This is valid only when the first segment TDES0 28 is set 28 FS First Segment When set this bit indicates that the buffer contains the first segment of a frame 29 LS Last Segment When set this bit ind...

Page 896: ...word 3 TDES3 Bit Symbol Description 31 0 B2ADD Buffer 2 Address Pointer Next Descriptor Address Indicates the physical address of Buffer 2 when a descriptor ring structure is used If the Second Addres...

Page 897: ...d in Table 660 The contents of RDES1 through RDES3 are identified in Table 661 to Table 663 Fig 90 Receive descriptor fields alternate configuration O W N Status 30 0 Buffer 1 Address 31 0 Buffer 2 Ad...

Page 898: ...ror can be of less no extension or error rxd 0f during extension 4 RWT Receive Watchdog Timeout When set this bit indicates that the Receive Watchdog Timer has expired while receiving the current fram...

Page 899: ...6 Late Collision RDES0 7 Giant Frame RDES4 4 3 IP Header Payload Error RDES0 11 Overflow Error RDES0 14 Descriptor Error This field is valid only when the Last Descriptor RDES0 8 is set 29 16 FL Fram...

Page 900: ...iple of 4 the resulting behavior is undefined This field is not valid if RDES1 14 is set See Section 28 7 6 1 3 for further details on calculating buffer sizes Table 662 Receive descriptor fields 2 RD...

Page 901: ...received 0000 No PTP message received 0001 SYNC all clock types 0010 Follow_Up all clock types 0011 Delay_Req all clock types 0100 Delay_Resp all clock types 0101 Pdelay_Req in peer to peer transpare...

Page 902: ...r 28 LPC43xx LPC43Sxx Ethernet Table 666 Receive descriptor fields 7 RDES7 Bit Symbol Description 31 0 RTSH Receive Frame Timestamp High This field is updated by DMA with the most significant 32 bits...

Page 903: ...l color STN displays Supports Thin Film Transistor TFT color displays Programmable display resolution including but not limited to 320x200 320x240 640x200 640x240 640x480 800x600 and 1024x768 Hardware...

Page 904: ...de palette RAM gray or color value In the case of STN displays either a value obtained from the addressed palette location or the true value is passed to the gray scaling generators The hardware coded...

Page 905: ...ulse width Number of lines per panel Number of pixel clocks per line Hardware cursor control Signal polarity active HIGH or LOW AC panel bias Panel clock frequency Bits per pixel Fig 91 LCD controller...

Page 906: ...or removes the requirement for this management by providing a completely separate image buffer for the cursor and superimposing the cursor image on the LCD output stream at the current cursor X Y coor...

Page 907: ...2 colors selected from 3375 2 bpp palettized 4 colors selected from 3375 4 bpp palettized 16 colors selected from 3375 8 bpp palettized 256 colors selected from 3375 16 bpp direct 4 4 4 RGB with 4 bpp...

Page 908: ...ower panel data LCDLP Output Line synchronization pulse STN Horizontal synchronization pulse TFT LCDVD 23 0 Output LCD panel data Bits used depend on the panel configuration GP_CLKIN Input General pur...

Page 909: ...displays Pin name 12 bit 4 4 4 mode 18 pins 16 bit 5 6 5 mode 22 pins 16 bit 1 5 5 5 mode 24 pins 24 bit 30 pins LCDPWR Y Y Y Y LCDDCLK Y Y Y Y LCDENAB LCDM Y Y Y Y LCDFP Y Y Y Y LCDLE Y Y Y Y LCDLP...

Page 910: ...O 0x028 Interrupt Clear register 0x0 Table 683 UPCURR RO 0x02C Upper Panel Current Address Value register 0x0 Table 684 LPCURR RO 0x030 Lower Panel Current Address Value register 0x0 Table 685 0x034 t...

Page 911: ...is a 6 bit value that represents between 16 and 1024 pixels per line PPL counts the number of pixel clocks that occur before the HFP is applied Program the value required divided by 16 minus 1 Actual...

Page 912: ...onization pulse Program the register with the number of lines required minus one The number of horizontal synchronization lines must be small for example program to zero for passive STN LCDs The highe...

Page 913: ...PCD 4 LCDDCLK LCDCLK 6 Single panel monochrome 4 bit interface mode PCD 2 LCDDCLK LCDCLK 4 Dual panel monochrome 4 bit interface mode and single panel monochrome 8 bit interface mode PCD 6 LCDDCLK LCD...

Page 914: ...s an enable that indicates to the LCD panel when valid display data is available In active display mode data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its...

Page 915: ...controller The base address must be doubleword aligned Optionally the value may be changed mid frame to create double buffered video displays These registers are copied to the corresponding current r...

Page 916: ...cription Reset value 0 LCDEN LCD enable control bit 0 LCD disabled Signals LCDLP LCDDCLK LCDFP LCDENAB and LCDLE are low 1 LCD enabled Signals LCDLP LCDDCLK LCDFP LCDENAB and LCDLE are high See LCD po...

Page 917: ...1 LCDPWR LCD power enable 0 power not gated through to LCD panel and LCDV 23 0 signals disabled held LOW 1 power gated through to LCD panel and LCDV 23 0 signals enabled active See LCD power up and po...

Page 918: ...when the LCD base address registers have been updated from the next address registers 0x0 3 VCOMPIM Vertical compare interrupt enable 0 The vertical compare time interrupt is disabled 1 Interrupt wil...

Page 919: ...Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 681 Raw Interrupt Status register INTRAW address 0x4000 8020 bit description Bit S...

Page 920: ...it Symbol Description Reset value 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 1 FUFIC FIFO underflow interrupt clear Writing a 1 t...

Page 921: ...ter see Cursor Configuration register description the cursor image RAM contains either four 32x32 cursor images or a single 64x64 cursor image The two colors defined for the cursor are mapped onto val...

Page 922: ...CrsrFrameSync is 0 the cursor image index is changed immediately even if the cursor is currently being scanned 29 6 17 Cursor Configuration register The CRSR_CFG register provides overall configuratio...

Page 923: ...e displayed according to the abilities of the LCD panel in the same way as the frame buffers palette output is displayed In monochrome STN mode only the upper 4 bits of the Red field are used In STN c...

Page 924: ...e CRSR_CFG register is 1 the displayed cursor image is only changed during the vertical frame blanking period providing that the cursor position has been updated since the Clip register was programmed...

Page 925: ...efined 13 8 CRSRCLIPY Cursor clip position for Y direction Distance from the top of the cursor image to the first displayed pixel in the cursor When 0 the first displayed pixel is from the top line of...

Page 926: ...ternal memory 29 7 1 1 AMBA AHB slave interface The AHB slave interface connects the LCD controller to the AHB bus and provides CPU accesses to the registers and palette RAM Table 696 Cursor Raw Inter...

Page 927: ...FIFOs It inserts busy cycles if the FIFOs have not completed their synchronization and updating sequence Fills up the DMA FIFOs in dual panel mode in an alternating fashion from a single DMA request A...

Page 928: ...ions For each of the three supported data formats the required data for each panel display pixel must be extracted from the data word Table 698 FIFO bits for Little endian Byte Little endian Pixel ord...

Page 929: ...LCD Table 699 FIFO bits for Big endian Byte Big endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 31 p0 p0 p0 p0 p0 30 p1 29 p2 p1 28 p3 27 p4 p2 p1 26 p5 25 p6 p3 24 p7 23 p8 p4 p2 p...

Page 930: ...he data in each DMA FIFO word in RGB mode Table 700 FIFO bits for Little endian Byte Big endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 31 p24 p12 p6 p3 p1 30 p25 29 p26 p13 28 p27...

Page 931: ...p1 Blue 1 p1 Blue 0 p1 Blue 3 26 p1 Blue 0 p1 Green 5 p1 Blue 2 25 p1 Green 4 p1 Green 4 p1 Blue 1 24 p1 Green 3 p1 Green 3 p1 Blue 0 23 p0 Blue 7 p1 Green 2 p1 Green 2 p1 Green 3 22 p0 Blue 6 p1 Gre...

Page 932: ...output of the pixel serializer is used as the TFT panel data The red and blue pixel data can be swapped to support BGR data format using a control register bit bit 8 BGR See the CTRL register descrip...

Page 933: ...lave interface This also provides a read write port to the cursor image RAM 29 7 5 1 Cursor operation The hardware cursor is contained in a dual port RAM It is programmed by software through the AHB s...

Page 934: ...or sizes are supported as shown in Table 705 29 7 5 3 Cursor movement The following descriptions assume that both the screen and cursor origins are at the top left of the visible screen the first visi...

Page 935: ...creen image The cursor image is clipped automatically at the screen limits when it extends beyond the screen image to the right or bottom see X1 Y1 in Figure 93 The checked pattern shows the visible p...

Page 936: ...register description in this chapter The displayed cursor coordinate system is expressed in terms of X Y 64 x 64 is an extension of the 32 x 32 format shown in Figure 94 32 by 32 pixel format Four cur...

Page 937: ...4 31 20 31 13 12 5 0 21 0 5 y 21 y 5 31 21 31 11 10 6 0 22 0 6 y 22 y 6 31 22 31 9 8 7 0 23 0 7 y 23 y 7 31 23 31 7 6 0 0 16 0 0 y 16 y 0 31 16 31 5 4 1 0 17 0 1 y 17 y 1 31 17 31 3 2 2 0 18 0 2 y 18...

Page 938: ...and lower panel formatters Formatters are used in STN mode to convert the gray scaler output to a parallel format as required by the display For monochrome displays this is either 4 or 8 bits wide an...

Page 939: ...rate of the LCD panel being used The CLKSEL bit in the POL register determines whether the base clock used is CCLK or the LCDCLKIN pin 29 7 9 Timing controller The primary function of the timing contr...

Page 940: ...may be cleared by writing a 1 to the BERIC bit in the INTCLR register This action releases the master interface from its ERROR state to the start of FRAME state and enables fresh frame of data display...

Page 941: ...have stabilized the contrast voltage not controlled or supplied by the LCD controller is applied to the LCD panel 4 If required a software or hardware timer can be used to provide the minimum display...

Page 942: ...10 December 2015 942 of 1441 NXP Semiconductors UM10503 Chapter 29 LPC43xx LPC43Sxx LCD Fig 95 Power up and power down sequences LCDLP LCDCP LCDFP LCDAC LCDLE LCD Power Contrast Voltage LCDPWR LCD 23...

Page 943: ...ected and scaled by the LCD controller and used to produce LCDCLK 3 The duration of the LCDLP signal is controlled by the HSW field in the TIMH register 4 The Polarity of the LCDLP signal is determine...

Page 944: ...ntal lines for one frame see horizontal timing for STN displays panel data clock active 1 The active data lines will vary with the type of TFT panel 2 The LCD panel clock is selected and scaled by the...

Page 945: ...se back porch defined in line clocks front porch defined in line clocks pixel data and horizontal control signals for one frame one frame all horizontal lines for one frame see horizontal timing for T...

Page 946: ...DPWR P7_7 LCDPWR P7_7 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN Table 711 LCD panel connections for STN single panel mode External pin 4 bit mono STN single panel 8 bit mono STN single...

Page 947: ...LPC43xx pin used LCD function Table 713 LCD panel connections for TFT panels External pin TFT 12 bit 4 4 4 mode TFT 16 bit 5 6 5 mode TFT 16 bit 1 5 5 5 mode TFT 24 bit LPC43xx pin used LCD function L...

Page 948: ...B LCDM P4_6 LCDENAB LCDM P4_6 LCDENAB LCDM P4_6 LCDENAB L CDM LCDFP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK LCDLE P7_0 LCDLE P7_0 LCDLE...

Page 949: ...REG block see Table 101 The SCT outputs are ORed with various timer match outputs if bit CTOUTCTRL in CREG6 is zero see Table 105 this is the default Set the CTOUTCTRL bit to one to use the SCT output...

Page 950: ...ption is whether a SCT operates as two 16 bit counters or a unified 32 bit counter In the two counter case in addition to the counter value the following operational elements are independent for each...

Page 951: ...sources Each SCT input is connected to one GIMA register which defines the input source Remark SCT outputs are connected to the CTOUT_n pins and are ORed with timer match outputs when the CTOUCTRL bi...

Page 952: ...T input 3 CTIN_3 yes USART0 TX active no I2S1_RX_MWS no I2S1_TX_MWS no SCT input 4 CTIN4 yes USART0 RX active no I2S1_RX_MWS no I2S1_TX_MWS no SCT input 5 CTIN_5 yes USART2 TX active no SGPIO12_DIV SC...

Page 953: ...art1 input ADC CR register bit START 0x3 1 SCT output 9 ORed with Timer3 match output 3 CTOUT_9 0 SCT output 9 CTOUT_9 1 SCT output 10 ORed with Timer3 match output 3 CTOUT_10 0 SCT output 10 CTOUT_10...

Page 954: ...4000 0000 Name Access Address offset Description Reset value Reference CONFIG R W 0x000 SCT configuration register 0x0000 7E00 Table 717 CTRL R W 0x004 SCT control register 0x0004 0004 Table 718 CTRL_...

Page 955: ...000 Table 734 CONFLAG R W 0x0FC SCT conflict flag register 0x0000 0000 Table 735 MATCH0 to MATCH15 R W 0x100 to 0x13C SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 0 0x0000 0...

Page 956: ...15 1 0x0000 0000 Table 739 MATCHREL0_L to MATCHREL15_L R W 0x280 to 0x2A0 MATCHREL alias registers see Section 30 7 9 SCT match reload value register 0 to 15 low counter 16 bit REGMOD0_L 0 to REGMODE1...

Page 957: ...00 0000 Table 741 EVSTATEMSK14 R W 0x370 SCT event state register 14 0x0000 0000 Table 740 EVCTRL14 R W 0x374 SCT event control register 14 0x0000 0000 Table 741 EVSTATEMSK15 R W 0x378 SCT event state...

Page 958: ...e 743 OUTPUTSET14 R W 0x570 SCT output 14 set register 0x0000 0000 Table 742 OUTPUTCL14 R W 0x574 SCT output 14 clear register 0x0000 0000 Table 743 OUTPUTSET15 R W 0x578 SCT output 15 set register 0x...

Page 959: ...nput 4 0x9 Falling edges on input 4 0xA Rising edges on input 5 0xB Falling edges on input 5 0xC Rising edges on input 6 0xD Falling edges on input 6 0xE Rising edges on input 7 0xF Falling edges on i...

Page 960: ...1 The counter counts up to its limit then counts down to 0 12 5 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock The counter clock is clocked at...

Page 961: ...and HALT_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation Remark Any event halting the counter disables its operation until software clea...

Page 962: ...ther registers Attempting to write a counter while it is running does not affect the counter but produces a bus error Software can read the counter registers at any time 30 6 8 SCT state register If U...

Page 963: ...the value of the state variable remains zero which is the default value A state variable can be used to track and control multiple cycles of the associated counter in any desired operational sequence...

Page 964: ...atch Capture register has an accompanying register which serves as a Reload register when the register is used as a Match register Section 30 6 21 or as a Capture Control register when the register is...

Page 965: ...5 bit 15 0 registers operate as match registers 1 registers operate as capture registers 0 31 16 REGMOD_H Each bit controls one pair of match capture registers register 0 bit 16 register 1 bit 17 regi...

Page 966: ...eversed when counter L or the unified counter is counting down 0x2 Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 15 14 SETCLR7 Set clear operation on output 7 Value...

Page 967: ...unter is counting down 0x2 Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 29 28 SETCLR14 Set clear operation on output 14 Value 0x3 is reserved Do not program this va...

Page 968: ...t and clear on output 5 0 0x0 No change 0x1 Set output or clear based on the SETCLR5 field 0x2 Clear output or set based on the SETCLR5 field 0x3 Toggle output 13 12 O6RES Effect of simultaneous set a...

Page 969: ...LR11 field 0x2 Clear output or set based on the SETCLR11 field 0x3 Toggle output 25 24 O12RES Effect of simultaneous set and clear on output 12 0 0x0 No change 0x1 Set output or clear based on the SET...

Page 970: ...he Match_L Unified registers from the Reload_L Unified registers 31 DRQ0 This read only bit indicates the state of DMA Request 0 Table 731 SCT DMA 1 request register DMAREQ1 address 0x4000 0060 bit de...

Page 971: ...ter is running does not affect the Match register and results in a bus error Match events occur in the SCT clock in which the counter is or would be incremented to the next value When a Match event li...

Page 972: ...Y 1 read or write the lower 16 bits of the 32 bit value to be compared to the unified counter 0 31 16 MATCHn_H When UNIFY 0 read or write the 16 bit value to be compared to the H counter When UNIFY 1...

Page 973: ...register to enable an event Since the state always remains at its reset value of 0 writing 0x01 effectively permanently state enables this event 30 6 24 SCT event control registers 0 to 15 This regis...

Page 974: ...5 bit description Bit Symbol Value Description Reset value 3 0 MATCHSEL Selects the Match register associated with this event if any A match can occur only when the counter selected by the HEVENT bit...

Page 975: ...TE the carry out is ignored 1 STATEV value is loaded into STATE 19 15 STATEV This value is loaded into or added to the state selected by HEVENT depending on STATELD when this event is the highest numb...

Page 976: ...30 7 1 Match logic 30 7 2 Capture logic 30 7 3 Event selection State variables allow control of the SCT across more than one cycle of the counter Counter matches input output edges and state values a...

Page 977: ...5 Interrupt generation The SCT generates one interrupt to the NVIC Fig 104 Event selection select event i select MATCHSELi inputs IOSELi select STATEMASKi COMBMODEi IOCONDi outputs OUTSELi HEVENTi H...

Page 978: ...mplicated by the prescaler and by clock mode 01 in which the SCT clock is the bus clock However the prescaler and counter are enabled to count only when a selected edge is detected on a clock input Th...

Page 979: ...est is connected If the Linked List feature is used there is a TransferSize value in each Linked List entry The GPDMA asserts the DMACCLR signal when that number of transfers has been completed which...

Page 980: ...anual Rev 2 1 10 December 2015 980 of 1441 NXP Semiconductors UM10503 Chapter 30 LPC43xx LPC43Sxx State Configurable Timer SCT MATCHREL1_L CAPCTRL1_L 0x204 0x282 MATCHREL1_H CAPCTRL1_H 0x206 0x2C2 Tab...

Page 981: ...cycles of the counter events can change the state multiple times and thus create a large variety of event controlled transitions on the SCT outputs and or interrupts Once configured the SCT can run co...

Page 982: ...ts set or clear this output More than one event can change the output and each event can change multiple outputs 3 Define how each event affects the counter Set the corresponding event bit in the LIMI...

Page 983: ...apture the counter contents when one or more events occur If the counter is in bidirectional mode the effect of set and clear of an output can be made to depend on whether the counter is counting up o...

Page 984: ...ing the STATE register To change the current state by software that is independently of any event occurring set the HALT bit and write to the STATE register to change the state value Writing to the ST...

Page 985: ...ction 30 2 Basic configuration Section 30 4 General description Section 30 5 Pin description Section 30 7 Functional description for all common SCT features 31 2 Features Two 16 bit counters or one 32...

Page 986: ...ure and capture control registers The register overview includes the alias registers for the Match Reload Fractional match Fractional match reload Capture and Capture Control L and H 16 bit registers...

Page 987: ...unter direction control register 0x0000 0000 Table 759 RES R W 0x058 SCT conflict resolution register 0x0000 0000 Table 760 DMAREQ0 R W 0x05C SCT DMA request 0 register 0x0000 0000 Table 761 DMAREQ1 R...

Page 988: ...16 bit 0x0000 0000 Table 768 MATCHREL0 to MATCHREL15 R W 0x200 to 0x23C SCT match reload value register 0 to 15 REGMOD0 0 to REGMODE15 0 0x0000 0000 Table 770 MATCHREL0_L to MATCHREL15_L R W 0x200 to...

Page 989: ...4 EV4_STATE R W 0x320 SCT event state register 4 0x0000 0000 Table 773 EV4_CTRL R W 0x324 SCT event control register4 0x0000 0000 Table 774 EV5_STATE R W 0x328 SCT event state register 5 0x0000 0000 T...

Page 990: ...Table 776 OUT6_SET R W 0x530 SCT output 6 set register 0x0000 0000 Table 775 OUT6_CLR R W 0x534 SCT output 6 clear register 0x0000 0000 Table 776 OUT7_SET R W 0x538 SCT output 7 set register 0x0000 0...

Page 991: ...ising edges on input 0 0x1 Falling edges on input 0 0x2 Rising edges on input 1 0x3 Falling edges on input 1 0x4 Rising edges on input 2 0x5 Falling edges on input 2 0x6 Rising edges on input 3 0x7 Fa...

Page 992: ...leared to zero in uni directional mode or to change the direction of count in bi directional mode Software can write to set or clear this bit at any time This bit is not used when the UNIFY bit is set...

Page 993: ...clocked at the rate of the SCT clock divided by PRE_L 1 Remark Clear the counter by writing a 1 to the CLRCTR bit whenever changing the PRE value 0 15 13 Reserved 16 DOWN_H This bit is 1 when the H c...

Page 994: ...G register this register can be written to as two registers START_L and START_H Both the L and H registers can be read or written individually or in a single 32 bit read or write operation Table 749 S...

Page 995: ...r cycle It is possible using this register to alter that behavior by qualifying the advancement through the dither pattern with designated events As with the other condition mask registers HALT STOP L...

Page 996: ...LT is 0 a write attempt does not change the state and results in a bus error The state variable is the main feature that distinguishes the SCT from other counter timer PWM blocks Events can be made to...

Page 997: ...le values for the state variable The change of the state variable during multiple counter cycles reflects how the associated state machine moves from one state to the next 31 3 10 SCT input register S...

Page 998: ...used only when the UNIFY bit is 0 An alternate addressing mode is available for all of the Match Capture and Reload Capture Control registers for DMA access to halfword registers when UNIFY 0 This mod...

Page 999: ...ear are reversed when counter H is counting down Do not use if UNIFY 1 3 2 SETCLR1 Set clear operation on output 1 Value 0x3 is reserved Do not program this value 0 0x0 Independent Set and clear do no...

Page 1000: ...lear operation on output 8 Value 0x3 is reserved Do not program this value 0 0x0 Independent Set and clear do not depend on any counter 0x1 L counter Set and clear are reversed when counter L or the u...

Page 1001: ...nd on any counter 0x1 L counter Set and clear are reversed when counter L or the unified counter is counting down 0x2 H counter Set and clear are reversed when counter H is counting down Do not use if...

Page 1002: ...set and clear on output 4 0 0x0 No change 0x1 Set output or clear based on the SETCLR4 field 0x2 Clear output or set based on the SETCLR4 field 0x3 Toggle output 11 10 O5RES Effect of simultaneous set...

Page 1003: ...of simultaneous set and clear on output 11 0 0x0 No change 0x1 Set output or clear based on the SETCLR11 field 0x2 Clear output or set based on the SETCLR11 field 0x3 Toggle output 25 24 O12RES Effec...

Page 1004: ...s the Match_L Unified registers from the Reload_L Unified registers 31 DRQ0 This read only bit indicates the state of DMA Request 0 Table 762 SCT DMA 1 request register DMAREQ1 address 0x4000 0060 bit...

Page 1005: ...d counter is running does not affect the Match register and results in a bus error Match events occur in the SCT clock in which the counter is or would be incremented to the next value When a Match ev...

Page 1006: ...tional Match Reload register associated with it The contents of the reload registers are transferred into the Fractional Match registers at the start of every new SCT counter cycle unless the NORELOAD...

Page 1007: ...nal match register 0 15 4 Reserved 19 16 FRACMAT_H When UNIFY 0 read or write 4 bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register n 0 to 5 0 31 20 Reserved T...

Page 1008: ...ate mask registers 0 to 15 Each event has one associated SCT event state mask register that allows this event to happen in one or more states of the counter selected by the HEVENT bit in the correspon...

Page 1009: ...gister In BIDR mode events can also be enabled based on the count direction Each event can modify its counter STATE value If more than one event associated with the same counter occurs in a given cloc...

Page 1010: ...e highest numbered event occurring for that state 0 0 STATEV value is added into STATE the carry out is ignored 1 STATEV value is loaded into STATE 19 15 STATEV This value is loaded into or added to t...

Page 1011: ...counter cycle i e when the counter counts down to zero in bi directional mode or is cleared to zero by a limit event the dither engine determines which matches are to be delayed by one clock during t...

Page 1012: ...Capture and Capture Control registers are arranged as consecutive words with the standard division of each word into two halfwords When the UNIFY bit is zero these two halfwords are related to the L a...

Page 1013: ...e same output but triggered by different match values If input 0 is found HIGH by the next time the timer is reset the associated event EV5 causes the state to change back to state 0where the events E...

Page 1014: ...IR_L 0 Clock base CONFIG Uses default values for clock configuration Match Capture registers REGMODE Configure one match register for each match event by setting REGMODE_L bits 0 1 2 3 4 to 0 This is...

Page 1015: ...ses match register 0 to qualify the event Define how event 5 changes the state EVCTRL5 Set STATEV bits to 0 and the STATED bit to 1 Event 5 changes the state to state 0 Define by which events output 0...

Page 1016: ...Pm input in the SCU Section 17 3 11 and then configure the capture input multiplexer for the selected pin through the GIMA see Section 18 3 The timer match outputs are connected to dedicated Tn_MATm p...

Page 1017: ...inputs to trap the timer value when an input signal transitions optionally generating an interrupt Table 781 gives a brief summary of each of the Timer Counter related functions 32 4 1 Architecture Th...

Page 1018: ...08 Timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 3 CAPTURE REGISTER 2 CAPTURE REGISTER 1 CAPTURE REGISTER 0 MATCH REGISTER 3 M...

Page 1019: ...to the Tn_MATm pin functions In addition the match outputs ORed with the SCT outputs can be monitored on the CTOUT pins provided that the CTOUTCTRL bit is set to 0 default in the CREG6 register see T...

Page 1020: ...ternal signal Default see GIMA Table 208 CTOUTCTRL bit see Table 105 Timer1 inputs CAP0 CTIN_0 yes SGPIO12 no T1_CAP0 no CAP1 CTIN_3 yes T1_CAP1 no USART0 TX active no CAP2 CTIN_4 yes T1_CAP2 no CAP3...

Page 1021: ...AP0 no CAP1 CTIN_1 yes T2_CAP1 no USART2 TX active no CAP2 I2S1_RX_MWS no CTIN_5 yes CAP3 T2_CAP2 no USART2 RX active no I2S1_TX_MWS no SCT output 7 OR T1 match channel 3 yes 0 SCT output 7 yes 1 T1 m...

Page 1022: ..._MWS no CAP2 CTIN_7 yes T3_CAP2 no USART3 RX active no SOF0 no CAP3 T3_CAP3 no SCT output 11 OR T2 match channel 3 yes 0 SCT output 11 yes 1 T2 match channel 3 no SOF1 no Timer3 outputs MAT0 T3_MAT0 M...

Page 1023: ...R is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface 0 Table 791 MCR R W 0x014 Match Control Register The MCR is used to control if...

Page 1024: ...00 This event does not cause an interrupt but a match register can be used to detect an overflow if needed Table 787 Timer interrupt registers IR addresses 0x4008 4000 TIMER0 0x4008 5000 TIMER1 0x400C...

Page 1025: ...control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 792 Table 789 Timer counter registers TC addresses 0x...

Page 1026: ...ed 1 Match Interrupt is generated when MR2 matches the value in the TC 7 MR2R Reset on MR2 0 0 Disabled Feature disabled 1 Match TC will be reset if MR2 matches it 8 MR2S Stop on MR2 0 0 Disabled Feat...

Page 1027: ...bits for that input in this register should be programmed as 000 but capture and or interrupt can be selected for the other 3 CAP inputs Table 793 Timer match registers MR 0 3 addresses 0x4008 4018 MR...

Page 1028: ...o high A sequence of 0 then 1 on CAPn 2 will cause CR2 to be loaded with the contents of TC 7 CAP2FE Capture on CAPn 2 falling edge 0 0 Disabled This feature is disabled 1 High to low A sequence of 1...

Page 1029: ...curs between the TC and MR0 this bit can either toggle go low go high or do nothing depending on bits 5 4 of this register This bit can be driven onto a MATn 0 pin in a positive logic manner 0 low 1 h...

Page 1030: ...inned out 0x2 Set Set the corresponding External Match bit output to 1 MATn m pin is HIGH if pinned out 0x3 Toggle Toggle the corresponding External Match bit output 11 10 EMC3 External Match Control...

Page 1031: ...addresses 0x4008 4070 TIMER0 0x4008 5070 TIMER1 0x400C 3070 TIMER2 0x400C 4070 TIMER3 bit description Bit Symbol Value Description Reset value 1 0 CTMODE Counter Timer Mode This field selects which ri...

Page 1032: ...ble bit in TCR is cleared and the interrupt indicating that a match occurred is generated 32 7 2 DMA operation DMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits of ea...

Page 1033: ...rison 33 4 Features The MCPWM contains three independent channels each including a 32 bit Timer Counter TC a 32 bit Limit register LIM a 32 bit Match register MAT a 10 bit dead time register DT and an...

Page 1034: ...nts on each processor clock or input pin transition until it reaches 0 at which time it starts counting up again Each channel also includes a Match register that holds a smaller value than the Limit r...

Page 1035: ...Clock selection TC0 Event selection TC1 Event selection TC2 Event selection MCCNTCON MCCAPCON MAT0 oper MAT0 write LIM0 oper LIM0 write CAP0 channel output control dead time counter DT0 A0 B0 MCCON R...

Page 1036: ...CON RO 0x000 PWM Control read address 0 Table 802 CON_SET WO 0x004 PWM Control set address Table 803 CON_CLR WO 0x008 PWM Control clear address Table 804 CAPCON RO 0x00C Capture Control read address...

Page 1037: ...Register overview Motor Control Pulse Width Modulator MCPWM base address 0x400A 0000 Name Access Address offset Description Reset value Reference Table 802 MCPWM Control read address CON 0x400A 0000...

Page 1038: ...d MCOB2 pins 0 0 Passive state is LOW active state is HIGH 1 Passive state is HIGH active state is LOW 19 DTE2 Controls the dead time feature for channel 1 0 0 Dead time disabled 1 Dead time enabled 2...

Page 1039: ...ponding bit in the CON register 8 RUN1_SET Writing a one sets the corresponding bit in the CON register 9 CENTER1_SET Writing a one sets the corresponding bit in the CON register 10 POLA1_SET Writing...

Page 1040: ..._CLR Writing a one clears the corresponding bit in the CON register 20 DISUP2_CLR Writing a one clears the corresponding bit in the CON register 28 2 1 Writing a one clears the corresponding bit in th...

Page 1041: ...1 TC2 is reset by a channel 2 capture event 0 31 21 Reserved Table 805 MCPWM Capture Control read address CAPCON 0x400A 000C bit description Bit Symbol Description Reset value Table 806 MCPWM Capture...

Page 1042: ...one sets the corresponding bits in the CAPCON register 31 21 Reserved Table 806 MCPWM Capture Control set address CAPCON_SET 0x400A 0010 bit description Bit Symbol Description Reset value Table 807 M...

Page 1043: ...gins counting up again 10 CAP1MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register 11 CAP1MCI2_FE_CLR Writing a one clears the corresponding bits in the CAPCON register 12 CA...

Page 1044: ...isters until software stops the channel Reading an LIM address always returns the operating value Remark In timer mode the period of a channel s modulated MCO outputs is determined by its Limit regist...

Page 1045: ...annel s MCO outputs at the state B active A passive write its Match register with a higher value than you write to its Limit register The match never occurs To lock a channel s MCO outputs at the oppo...

Page 1046: ...nly but the underlying registers can be cleared by writing to the CAP_CLR address 33 7 9 MCPWM Interrupt registers The Motor Control PWM module includes the following interrupt sources Table 812 MCPWM...

Page 1047: ...terrupts for channels 0 1 2 ABORT Fast abort interrupt Table 815 MCPWM Interrupt Enable read address INTEN 0x400A 0050 bit description Bit Symbol Value Description Reset value 0 ILIM0 Limit interrupt...

Page 1048: ...M interrupt enable set register INTEN_SET address 0x400A 0054 bit description Bit Symbol Description Reset value 0 ILIM0_SET Writing a one sets the corresponding bit in INTEN thus enabling the interru...

Page 1049: ...a one clears the corresponding bit in INTEN thus disabling the interrupt 2 ICAP0_CLR Writing a one clears the corresponding bit in INTEN thus disabling the interrupt 3 Reserved 4 ILIM1_CLR Writing a...

Page 1050: ...not affect counter 1 1 If MODE1 is 1 counter 1 advances on a rising edge on MCI0 7 TC1MCI0_FE Counter 1 falling edge mode channel 0 0 0 A falling edge on MCI0 does not affect counter 1 1 If MODE1 is 1...

Page 1051: ...MODE2 is 1 counter 2 advances on a falling edge on MCI2 28 18 Reserved 29 CNTR0 Channel 0 counter timer mode 0 0 Channel 0 is in timer mode 1 Channel 0 is in counter mode 30 CNTR1 Channel 1 counter ti...

Page 1052: ...er 14 TC2MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register 15 TC2MCI1_FE_SET Writing a one sets the corresponding bit in the CNTCON register 16 TC2MCI2_RE_SET Writing a one s...

Page 1053: ...corresponding bit in the CNTCON register 8 TC1MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register 9 TC1MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON r...

Page 1054: ...t to the Interrupt Controller 3 Reserved 4 ILIM1_F Limit interrupt flag for channel 1 0 0 This interrupt source is not contributing to the MCPWM interrupt request 1 If the corresponding bit in INTEN i...

Page 1055: ...06C bit description Bit Symbol Description Reset value 0 ILIM0_F_SET Writing a one sets the corresponding bit in the INTF register thus possibly simulating hardware interrupt 1 IMAT0_F_SET Writing a o...

Page 1056: ...one clears the corresponding bit in INTEN thus disabling the interrupt 3 Reserved 4 ILIM1_F_CLR Writing a one clears the corresponding bit in INTEN thus disabling the interrupt 5 IMAT1_F_CLR Writing...

Page 1057: ...s modulated MCO outputs is determined by its Limit register and the pulse width at the start of the period is determined by its Match register If it suits your way of thinking consider the Limit regi...

Page 1058: ...channel s A or B output changes from active to passive The transition of the other output from passive to active is delayed until the dead time counter reaches 0 During the dead time the MCOA and MCOB...

Page 1059: ...pdated immediately Software can write to a TC register only when its channel is stopped 33 8 3 Fast Abort ABORT The MCPWM has an external input MCABORT When this input goes low all six MCO outputs ass...

Page 1060: ...asked by a bit in the current commutation pattern register CP If a bit in the CP register is 0 its output pin has the logic level for the passive state of output MCOA0 The polarity of the off state is...

Page 1061: ...used Each channel controls its MCO output by comparing its MAT value to TC0 Figure 117 shows sample waveforms for the six MCO outputs in three phase AC mode The POLA bits are set to 0 for all three c...

Page 1062: ...n any channel captures the value of its TC into its Capture register because a selected edge occurs on any of MCI0 2 When all three channels outputs are forced to A passive state because the MCABORT p...

Page 1063: ...2X or 4X position counting Velocity capture using built in timer Velocity compare function with less than interrupt Uses 32 bit registers for position and velocity Three position compare registers wi...

Page 1064: ...ntal encoder converts angular displacement into two pulse signals By monitoring both the number of pulses and the relative phase of the two signals you can track the position direction of rotation and...

Page 1065: ...terface block diagram Digital Filter dir clk _ pulse Inx gating Windowing Inx_ pulse i dx Pha Phb Quad Decoder Velocity Counter Velocity Capture Velocity Compare Velocity Reload Velocity Timer tim _in...

Page 1066: ...Table 832 CMPOS0 R W 0x014 position compare register 0 0xFFFF FFFF Table 833 CMPOS1 R W 0x018 position compare register 1 0xFFFF FFFF Table 834 CMPOS2 R W 0x01C position compare register 2 0xFFFF FFFF...

Page 1067: ...apter 34 LPC43xx LPC43Sxx Quadrature Encoder Interface QEI INTSTAT RO 0xFE0 Interrupt status register 0 Table 851 IE RO 0xFE4 Interrupt enable register 0 Table 852 CLR WO 0xFE8 Interrupt status clear...

Page 1068: ...ion Bit Symbol Description Reset value 0 RESP Reset position counter When set 1 resets the position counter to all zeros Autoclears when the position counter is cleared 0 1 RESPI Reset position counte...

Page 1069: ...2 CAPMODE Capture Mode When 0 only PhA edges are counted 2X When 1 BOTH PhA and PhB edges are counted 4X increasing resolution but decreasing range 0 3 INVINX Invert Index When set inverts the sense...

Page 1070: ...r contains a position compare value This value is compared against the current value of the position register Interrupts can be enabled to interrupt when the compare value is less than equal to or gre...

Page 1071: ...ster CAP the timer is reloaded with the value stored in the velocity reload register LOAD and the velocity interrupt TIM_Int is asserted 34 6 2 10 QEI Velocity register This register contains the runn...

Page 1072: ...unt of zero bypasses the filter 34 6 2 14 QEI Digital filter on phase B input register This register contains the sampling count for the digital filter A sampling count of zero bypasses the filter 34...

Page 1073: ...upts can be enabled to interrupt when the compare value is less than equal to or greater than the current value of the index count register 34 6 2 18 QEI Index Compare register 2 This register contain...

Page 1074: ...rrent position 0 9 REV0_INT Indicates that the index 0 compare value is equal to the current index count 0 10 POS0REV_INT Combined position 0 and revolution count interrupt Set when both the POS0_INT...

Page 1075: ...served 0 Table 850 QEI Interrupt Enable Set register IES address 0x400C 6FDC bit description Bit Symbol Description Reset value Table 851 QEI Interrupt Status register INTSTAT address 0x400C 6FE0 bit...

Page 1076: ...index count 0 10 POS0REV_INT Combined position 0 and revolution count interrupt Set when both the POS0_INT bit is set and the REV0_INT is set 0 11 POS1REV_INT Combined position 1 and revolution count...

Page 1077: ...description Bit Symbol Description Reset value 0 INX_INT Indicates that an index pulse was detected 0 1 TIM_INT Indicates that a velocity timer overflow occurred 0 2 VELC_INT Indicates that captured...

Page 1078: ...e Table 828 When the SigMode bit 1 the quadrature decoder is bypassed and the PhA pin functions as the direction signal and PhB pin functions as the clock signal for the counters etc When the SigMode...

Page 1079: ...ntly enabled Alternatively the phase signals can be interpreted as a clock and direction signal as output by some encoders The position counter is automatically reset on one of three conditions Increm...

Page 1080: ...to 0 and 4 for CapMode set to 1 For example consider a motor running at 600 rpm A 2048 pulse per revolution quadrature encoder is attached to the motor producing 8192 phase edges per revolution With...

Page 1081: ...enerated when the counter value equals the compare value after masking This allows for combinations not possible with a simple compare 35 4 General description The Repetitive Interrupt Timer RIT provi...

Page 1082: ...EAK INTR PBUS PBUS PBUS RESET RESET RESET SET_INT 32 32 PBUS write 1 to clear PBUS PBUS CLR RESET CNT_ENA CTRL register CLR RESET ENABLE_CLK COMPARE register MASK register bit 0 MASK bit 31 MASK 32 X...

Page 1083: ...lways true 0 Table 862 RI Control register CTRL address 0x400C 0008 bit description Bit Symbol Value Description Reset value 0 RITINT Interrupt flag 0 1 This bit is set to 1 by hardware whenever the c...

Page 1084: ...FFFFFF it rolls over to 0x000 00000 on the next clock and continues counting If the enable_clr bit is set to 1 a valid comparison will also cause the counter to be reset to zero Counting will resume f...

Page 1085: ...ption The alarm timer is a 16 bit timer and counts down from a preset value The counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled The alarm timer operates in the R...

Page 1086: ...69 STATUS R 0xFE0 Status register 0x0 Table 870 ENABLE R 0xFE4 Enable register 0x0 Table 871 CLR_STAT W 0xFE8 Clear register 0x0 Table 872 SET_STAT W 0xFEC Set register 0x0 Table 873 Table 866 Downcou...

Page 1087: ...E0 bit description Bit Symbol Description Reset value 0 STAT A 1 in this bit shows that the STATUS interrupt has been raised 0 31 1 Reserved Table 871 Interrupt enable register ENABLE 0x4004 0FE4 bit...

Page 1088: ...nning read the Alarm timer counter register DOWNCOUNTER see Table 866 which counts down from a preset value using the 1024 Hz clock signal derived from the 32 kHz oscillator 37 3 Features Measures the...

Page 1089: ...arate 32 kHz oscillator that produces a 1 Hz internal time reference The RTC is powered by its own power supply pin VBAT 37 5 Pin description Fig 121 RTC functional block diagram day of year second mi...

Page 1090: ...8 Consolidated Time Register 1 1 Table 883 CTIME2 R 0x01C Consolidated Time Register 2 1 Table 884 SEC R W 0x020 Seconds Register 1 Table 887 MIN R W 0x024 Minutes Register 1 Table 888 HRS R W 0x028 H...

Page 1091: ...rrupt 0 1 RTCALF When one the alarm registers generated an interrupt Writing a one to this bit location clears the alarm interrupt 0 31 2 Reserved user software should not write ones to reserved bits...

Page 1092: ...e Second value generates an interrupt 0 1 IMMIN When 1 an increment of the Minute value generates an interrupt 0 2 IMHOUR When 1 an increment of the Hour value generates an interrupt 0 3 IMDOM When 1...

Page 1093: ...Description Reset value 5 0 SECONDS Seconds value in the range of 0 to 59 1 7 6 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 13 8 MI...

Page 1094: ...365 366 for leap years 1 31 12 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 885 Time Counter relationships and values Counter S...

Page 1095: ...MINUTES Minutes value in the range of 0 to 59 1 31 6 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 889 Hours register HRS addre...

Page 1096: ...The bits in this register are not changed by reset Table 892 Day of year register DOY address 0x4004 6034 bit description Bit Symbol Description Reset value 8 0 DOY Day of year value in the range of...

Page 1097: ...erved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 895 Calibration register CALIBRATION address 0x4004 6040 bit description Bit Symbol V...

Page 1098: ...nth value in the range of 1 to 28 29 30 or 31 depending on the month and whether it is a leap year 1 31 5 Reserved user software should not write ones to reserved bits The value read from a reserved b...

Page 1099: ...st the time counter either by not incrementing the counter or by incrementing the counter by 2 instead of 1 This allows calibrating the RTC oscillator under some typical voltage and temperature condit...

Page 1100: ...ycle If an alarm match event occurs in the same cycle as the calibration match the alarm interrupt will be delayed by one cycle to avoid a double alarm interrupt Forward calibration Enable the RTC tim...

Page 1101: ...and maximum time out period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Programmable 24 bit timer with internal fixed pre scaler Se...

Page 1102: ...FF to be loaded in the counter Hence the minimum Watchdog interval is TWDCLK 256 4 and the maximum Watchdog interval is TWDCLK 224 4 in multiples of TWDCLK 4 The Watchdog should be used in the followi...

Page 1103: ...lock the value of the counter on WDCLK and then synchronize it with the PCLK for reading when the TV register by the CPU 38 7 Register description The Watchdog registers are shown in Table 906 1 Reset...

Page 1104: ...watchdog interrupt occurs in Sleep or Deep sleep mode it will wake up the device Table 907 Watchdog Mode register MOD 0x4008 0000 bit description Bit Symbol Value Description Reset value 0 WDEN Watchd...

Page 1105: ...register other than writing 0x55 to FEED register causes an immediate reset interrupt when the Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following...

Page 1106: ...mer counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WDWARNINT is set to 0 the interrupt will occur at the same time as the watchdog event 38 7 6 Watchdog timer win...

Page 1107: ...is shown below in Figure 123 Table 913 Watchdog Timer Window register WINDOW 0x4008 0018 bit description Bit Symbol Description Reset value 23 0 WDWINDOW Watchdog window value 0xFF FFFF 31 24 Reserve...

Page 1108: ...1257 WDCLK 4 Watchdog Counter Early Feed Event Watchdog Reset Conditions WINDOW 0x1200 WARNINT 0x3FF TC 0x2000 Fig 124 Correct Watchdog Feed with Windowed Mode Enabled Correct Feed Event 1201 11FF 120...

Page 1109: ...edicated counter tracking the total number of events Timestamp values are taken from the RTC Runs in RTC power domain independent of system power supply Can run in Deep Power Down mode if VBAT is pres...

Page 1110: ...s a 1 2 ms rejection filter in case of the 1 kHz sample clock a 15 6 31 2 ms rejection filter in case of the 64 Hz sample clock and a 62 5 125ms rejection filter in case of the 16 Hz sample clock Such...

Page 1111: ...he CPU should ignore the timestamp registers if the ERSTATUS EVx bit is cleared There is no mechanism to clear or invalidate the timestamps after the event flag in the status register has been cleared...

Page 1112: ...7 Table 916 Register overview event monitor recorder base address 0x4004 6000 Name Access Address offset Description Reset value ERCONTROL R W 0x084 Event Monitor Recorder Control register Contains bi...

Page 1113: ...hould be written NA 10 INTWAKE_EN1 Interrupt and wake up enable for channel 1 0 0 No interrupt or wake up will be generated by event channel 1 1 An event in channel 1 will trigger an RTC interrupt and...

Page 1114: ...nt Monitor Recorder is disabled except for asynchronous clearing of GP registers if selected 0x1 16 Hz sample clock Enable Event Monitor Recorder and select a 16 Hz sample clock for event input edge d...

Page 1115: ...hannel1 Event flag WAKEUP1 pin Set at the end of any second if there has been an event during the preceding second This bit is cleared by writing a 1 to it Writing 0 has no effect 0 0 No event change...

Page 1116: ...nt occurs on each Event Monitor Recorder channel Contents of these register are only valid if the corresponding EVx bit in the ERSTATUS register 1 Table 919 Event Monitor Recorder Counters Register ER...

Page 1117: ...e the first event and the most recent event being the same The values will diverge if a second event occurs on the same channel Table 921 Event Monitor Recorder Last Stamp Register ERLASTSTAMP 0 2 0x0...

Page 1118: ...f the timers or the SCT In synchronous mode set the clock frequency on pin U0 2 3_UCLK to 6 BASE_UART0 2 3_CLK 40 3 Features 16 byte receive and transmit FIFOs Register locations conform to 550 indust...

Page 1119: ...await access by the CPU or host via the generic host interface The USART transmitter block TX accepts data written by the CPU or host and buffers the data in the USART TX Holding Register FIFO THR The...

Page 1120: ...ransmitter Shift Register Transmitter Holding Register Transmitter FIFO Transmitter Receiver Shift Register Receiver Buffer Register Receiver FIFO Receiver TX_DMA_REQ TX_DMA_CLR RX_DMA_REQ RX_DMA_CLR...

Page 1121: ...USART2 in synchronous mode USART3 U3_RXD I Serial Input Serial receive data U3_TXD O Serial Output Serial transmit data U3_DIR I O RS 485 EIA 485 output enable direction control U3_UCLK I O Serial cl...

Page 1122: ...storage for software 0x00 Table 935 ACR R W 0x020 Auto baud Control Register Contains controls for the auto baud feature 0x00 Table 936 ICR R W 0x024 IrDA control register USART3 only 0x00 Table 937 F...

Page 1123: ...he THR is always Write Only 40 6 3 USART Divisor Latch LSB and MSB Registers The USART Divisor Latch is part of the USART Baud Rate Generator and holds the value used along with the Fractional Divider...

Page 1124: ...baud rate of the USART 0x00 31 8 Reserved Table 929 USART Interrupt Enable Register when DLAB 0 IER addresses 0x4008 1004 USART0 0x400C 1004 USART2 0x400C 2004 USART3 bit description Bit Symbol Value...

Page 1125: ...it Symbol Value Description Reset value Table 930 USART Interrupt Identification Register read only IIR addresses 0x4008 1008 USART0 0x400C 1008 USART2 0x400C 2008 USART3 bit description Bit Symbol Va...

Page 1126: ...RT RDA interrupt IIR 3 1 010 shares the second level priority with the CTI interrupt IIR 3 1 110 The RDA is activated when the USART Rx FIFO reaches the trigger level defined in FCR7 6 and is reset wh...

Page 1127: ...the USART THR FIFO has held two or more characters at one time and currently the THR is empty The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs and the THRE is the highes...

Page 1128: ...CR determines the format of the data character that is to be transmitted or received 1 RXFIFORES RX FIFO Reset 0 0 No effect No impact on either of USART FIFOs 1 Clear Writing a logic 1 to FCR 1 will...

Page 1129: ...ing 1 Enable parity generation and checking 5 4 PS Parity Select 0 0x0 Odd parity Number of 1s in the transmitted character and the attached parity bit will be odd 0x1 Even Parity Number of 1s in the...

Page 1130: ...FCR0 Upon detection of a framing error the RX will attempt to re synchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next rec...

Page 1131: ...s valid data 1 Empty THR and the TSR are empty 7 RXFE Error in RX FIFO LSR 7 is set when a character with a RX error such as framing error parity error or break interrupt is loaded into the RBR This b...

Page 1132: ...automatically cleared after auto baud completion 1 MODE Auto baud mode select bit 0 0 Mode 0 1 Mode 1 2 AUTORESTART Restart bit 0 0 No restart 1 Restart Restart in case of time out counter restarts a...

Page 1133: ...to the specified fractional requirements Important If the fractional divider is active DIVADDVAL 0 and DLM 0 the value of the DLL register must be 3 or greater 1 IRDAINV Serial input direction 0 0 No...

Page 1134: ...these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided 40 6 13 USART Oversampling Register I...

Page 1135: ...e USART ensures that the receiver is locked when idle or will enter a locked state after having received a complete ongoing character reception Line conflicts must be handled in software The behavior...

Page 1136: ...USART2 0x400C 2048 USART3 bit description Bit Symbol Value Description Reset value 0 SCIEN Smart Card Interface Enable 0 0 Disabled Smart card interface disabled 1 Enabled synchronous half duplex sma...

Page 1137: ...time cycles to allow the smart card to process the information before sending a response The extra guard time can be programmed from 0 to 255 where 255 indicates the minimum possible character length...

Page 1138: ...tion this value is used to accept or reject serial input data 2 AADEN AAD enable 0 0 Disabled Auto Address Detect AAD is disabled 1 Enabled Auto Address Detect AAD is enabled 3 Reserved 4 DCTRL Direct...

Page 1139: ...gister works in conjunction with an 8 bit counter 0x00 31 8 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 946 USART Synchrono...

Page 1140: ...dware after having received a complete character This can be done by asserting the CCCLR bit This is useful in half duplex mode where the clock cannot be generated by sending a character After the rec...

Page 1141: ...by the ACR Mode bit In Mode 0 the baud rate is measured on two subsequent falling edges of the USART Rx pin the falling edge of the start bit and the falling edge of the least significant bit In Mode...

Page 1142: ...ocol will execute the following phases 1 On ACR Start bit setting the baud rate measurement counter is reset and the USART RSR is reset The RSR baud rate is switched to the highest rate 2 A falling ed...

Page 1143: ...and LSB are used for auto baud b Mode 1 only start bit is used for auto baud Fig 128 Auto baud a mode 0 and b mode 1 waveform UARTn RX start bit LSB of A or a U0ACR start rate counter start bit0 bit1...

Page 1144: ...lds a baud rate with a relative error of less than 1 1 from the desired one The USART baud rate can be calculated as 8 Where USART_PCLK is the peripheral clock DLM and DLL are the standard USART baud...

Page 1145: ...0 LPC43xx LPC43Sxx USART0_2_3 Fig 129 Algorithm for setting USART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integer DIVADDVAL 0 MULVAL 1 True FR est 1 5 DL est Int...

Page 1146: ...0 DLL 4 DIVADDVAL 5 and MULVAL 8 According to Equation 6 the USART s baud rate is 115384 This rate has a relative error of 0 16 from the originally specified 115200 40 7 4 RS 485 EIA 485 modes of ope...

Page 1147: ...o disable the receiver RS 485 EIA 485 Auto Address Detection AAD mode When both RS485CTRL register bits 0 9 bit mode enable and 2 AAD mode enable are set the USART is in auto address detect mode In th...

Page 1148: ...onfigured USART the serial interface is extended with a serial input and output clock and an output enable for controlling the clock pad By default transmission and reception in synchronous mode opera...

Page 1149: ...identified by the start and stop bits the serial clock is used to determine the data bits When the serial clock is running all data that is sampled is regarded as valid data In order to be able to ide...

Page 1150: ...terface but is clocked in the USART clock domain at the sampling edge of the serial clock During synchronous master mode when start and stop bits are transmitted the user can enable the external clock...

Page 1151: ...USART out of reset and enable clocking to the peripheral 2 Setup an available USART TXD pin for the bidirectional transfers 3 Set up the UCLK pin as the clock source using pin configuration registers...

Page 1152: ...em control handshaking available Data sizes of 5 6 7 and 8 bits Parity generation and checking odd even mark space or none One or two stop bits 16 byte Receive and Transmit FIFOs Built in baud rate ge...

Page 1153: ...Register FIFO THR The UART1 TX Shift Register TSR reads the data stored in the THR and assembles the data to transmit via the serial output pin TXD1 The UART1 Baud Rate Generator block BRG generates...

Page 1154: ...ster Transmitter Holding Register Transmitter FIFO Transmitter Receiver Shift Register Receiver Buffer Register Receiver FIFO Receiver TX_DMA_REQ TX_DMA_CLR RX_DMA_REQ RX_DMA_CLR Baud Rate Generator F...

Page 1155: ...or a priority level 4 interrupt if enabled IER 3 1 U1_DSR Input Data Set Ready Active low signal indicates if the external modem is ready to establish a communications link with the UART1 In normal op...

Page 1156: ...Register Contains individual interrupt enable bits for the 7 potential UART1 interrupts DLAB 0 0x00 Table 956 IIR RO 0x008 Interrupt ID Register Identifies which interrupt s are pending 0x01 Table 957...

Page 1157: ...access the THR The THR is write only 41 6 3 UART1 Divisor Latch LSB and MSB Registers when DLAB 1 The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used along with t...

Page 1158: ...rved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 956 UART1 Interrupt Enable Register when DLAB 0 IER address 0x4008 2004 bit descrip...

Page 1159: ...Disable end of auto baud Interrupt 1 Enable Enable end of auto baud Interrupt 9 ABTOIE Enables the auto baud time out interrupt 0 0 Disable Disable auto baud time out Interrupt 1 Enable Enable auto ba...

Page 1160: ...efined in FCR7 6 and is reset when the UART1 Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interr...

Page 1161: ...the THR is empty The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs and the THRE is the highest interrupt IIR 3 1 001 It is the lowest priority interrupt and is activated...

Page 1162: ...R determines the format of the data character that is to be transmitted or received 1 RXFIFORES RX FIFO Reset 0 0 No effect No impact on either of UART1 FIFOs 1 Clear Writing a logic 1 to FCR 1 will c...

Page 1163: ...parity bit will be odd 0x1 Even Parity Number of 1s in the transmitted character and the attached parity bit will be even 0x2 Force HIGH Forced 1 stick parity 0x3 Force LOW Forced 0 stick parity 6 BC...

Page 1164: ...pback mode 1 Enabled Enable modem loopback mode 5 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 0 6 RTSEN RTS enable 0 0 Disabled Disa...

Page 1165: ...the spacing state all zeroes for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to m...

Page 1166: ...0 0 No change No change detected on modem input CTS 1 State change State change detected on modem input CTS 1 DDSR Delta DSR Set upon state change of input DSR Cleared on an MSR read 0 0 No change No...

Page 1167: ...to baud run bit This bit is automatically cleared after auto baud completion 1 MODE Auto baud mode select bit 0 0 Mode 0 1 Mode 1 2 AUTORESTART Auto baud restart bit 0 0 No restart 1 Restart Restart i...

Page 1168: ...s disabled and the clock will not be divided 41 6 14 UART1 RS485 Control register The RS485CTRL register controls the configuration of the UART in RS 485 EIA 485 mode UART1baudrate PCLK 16 256 DLM DLL...

Page 1169: ...the polarity of the direction control signal on the RTS or DTR pin 0 0 Low The direction control pin will be driven to logic 0 when the transmitter has data to be sent It will be driven to logic 1 af...

Page 1170: ...it has begun sending the additional byte RTS1 is automatically reasserted to a low value once the receiver FIFO has reached the previous trigger level The re assertion of RTS1 signals to the sending...

Page 1171: ...e set though Table 971 lists the conditions for generating a Modem Status interrupt The auto CTS function reduces interrupts to the host system When flow control is enabled a CTS1 state change does no...

Page 1172: ...the pending transmission has completed The UART will continue transmitting a 1 bit as long as CTS1 is de asserted high As soon as CTS1 gets de asserted transmission resumes and a start bit is sent fo...

Page 1173: ...ansmit and receive 4 bit to 16 bit frame 42 4 General description The SSP is a Synchronous Serial Port SSP controller capable of operation on a SPI 4 wire SSI or Microwire bus It can interact with mul...

Page 1174: ...er according to the protocol in use When there is just one bus master and one bus slave the Frame Sync or Slave Select signal from the Master can be connected directly to the slave s corresponding inp...

Page 1175: ...W 0x024 SSP0 DMA control register 0 Table 985 Table 974 Register overview SSP0 base address 0x4008 3000 Name Access Address offset Description Reset value 1 Reference Table 975 Register overview SSP1...

Page 1176: ...bit transfer 0xF 16 bit transfer 5 4 FRF Frame Format 00 0x0 SPI 0x1 TI 0x2 Microwire 0x3 This combination is not supported and should not be used 6 CPOL Clock Out Polarity This bit is only used in S...

Page 1177: ...nes 3 SOD Slave Output Disable This bit is relevant only in slave mode MS 1 If it is 1 this blocks this SSP controller from driving the transmit data line MISO 0 31 4 Reserved user software should not...

Page 1178: ...word masked in the opposite sense from classic computer terminology in which masked meant disabled ARM uses the word masked to mean enabled To avoid confusion we will not use the word masked Table 97...

Page 1179: ...ive Time out condition occurs A Receive Time out occurs when the Rx FIFO is not empty and no has not been read for a time out period The time out period is the same for master and slave modes and is d...

Page 1180: ...his bit is 1 if the Rx FIFO is not empty has not been read for a time out period and this interrupt is enabled The time out period is the same for master and slave modes and is determined by the SSP b...

Page 1181: ...ext rising edge of CLK the MSB of the 4 bit to 16 bit data frame is shifted out on the DX pin Likewise the MSB of the received data is shifted onto the DR pin by the off chip serial slave device Table...

Page 1182: ...y control bit is 0 it produces a steady state low value on the SCK pin If the CPOL clock polarity control bit is 1 a steady state high value is placed on the CLK pin when data is not being transferred...

Page 1183: ...ransmission after all bits of the data word have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous...

Page 1184: ...a single word transfer after all bits have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transfers t...

Page 1185: ...transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must rai...

Page 1186: ...the off chip slave device During this transmission no incoming data is received by the SSP After the message has been sent the off chip slave decodes it and after waiting one serial clock after the la...

Page 1187: ...ceived data from the current frame Each of the received values is transferred from the receive shifter on the falling edge SK after the LSB of the frame has been latched into the SSP 42 7 3 1 Setup an...

Page 1188: ...t rate of one eighth of the peripheral clock rate 8 to 16 bits per transfer 43 4 General description SPI is a full duplex serial interface It can handle multiple masters and slaves being connected to...

Page 1189: ...10 December 2015 1189 of 1441 NXP Semiconductors UM10503 Chapter 43 LPC43xx LPC43Sxx SPI Fig 143 SPI block diagram MOSI_IN MOSI_OUT MISO_IN MISO_OUT OUTPUT ENABLE LOGIC SPI REGISTER INTERFACE SPI Inte...

Page 1190: ...is signal is not directly driven by the master It could be driven by a simple general purpose I O under software control Remark Note that this pin in an input pin only The SPI in master mode cannot dr...

Page 1191: ...l Value Description Reset value 1 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 2 BITENABLE 0 The SPI controller sends and receives...

Page 1192: ...r 0xE 14 bits per transfer 0xF 15 bits per transfer 0x0 16 bits per transfer 31 12 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Ta...

Page 1193: ...content of the SPCCR register is not relevant 6 WCOL Write collision When 1 this bit indicates that a write collision has occurred This bit is cleared by reading this register then accessing the SPI D...

Page 1194: ...x4010 000C bit description Bit Symbol Description Reset value 7 0 COUNTER SPI0 Clock counter setting 0x00 31 8 Reserved user software should not write ones to reserved bits The value read from a reser...

Page 1195: ...ram note two points First the SPI is illustrated with the Clock Polarity control bit CPOL in the SPI Control Register set to both 0 and 1 The second point to note is the activation and de activation o...

Page 1196: ...es inactive When a device is a slave and CPHA is set to 1 the transfer starts on the first clock edge when the slave is selected and ends on the last clock edge where data is sampled Fig 144 SPI data...

Page 1197: ...ister when a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data buffer where it is later read A read of the S...

Page 1198: ...done when a slave SPI transfer is not in progress 3 Wait for the SPIF bit in the SPI Status Register to be set to 1 The SPIF bit will be set after the last sampling clock edge of the SPI data transfe...

Page 1199: ...as selected the device to be a slave This condition is known as a mode fault When a mode fault is detected the mode fault MODF bit in the SPI Status Register will be activated the SPI signal drivers w...

Page 1200: ..._AUDIO_CLK The I2S0 1 MWS signals I2S0_RX_MWS I2S0_TX_MWS IS1_RX_MWS I2S1_TX_MWS can be connected to timer3 or the SCT through the GIMA see Table 208 44 3 Features The I2S bus provides a standard comm...

Page 1201: ...ormat for 8 bit 16 bit and 32 bit audio data both for stereo and mono modes Configuration data access and control is performed by a APB register set Data streams are buffered by FIFOs with a depth of...

Page 1202: ...ble 105 44 4 2 I2S connections to the GIMA The Word Select MWS signal is generated by the I2S blocks in slave and master mode to capture or generate data MWS either originates either from the pin mux...

Page 1203: ...2S0 1_RX_SDA Input Output Receive Data Serial data received MSB first It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I2S0 1_RX_MCLK...

Page 1204: ...er 44 LPC43xx LPC43Sxx I2S interface Fig 146 Simple I2S configurations and bus timing TRANSMITTER MASTER CONTROLLER MASTER TRANSMITTER SLAVE RECEIVER MASTER SCK serial clock WS word select SD serial d...

Page 1205: ...ack Register Contains status information about the I2S interface 0x7 Table 1005 DMA1 R W 0x014 I2S DMA Configuration Register 1 Contains control information for DMA request 1 0 Table 1006 DMA2 R W 0x0...

Page 1206: ...control information for DMA request 2 0 Table 1007 IRQ R W 0x01C I2S Interrupt Request Control Register Contains bits that control how the I2S interrupt request is generated 0 Table 1008 TXRATE R W 0...

Page 1207: ...ed user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 1001 I2S Digital Audio Output register DAO address 0x400A 2000 I2S0 and 0x400A 3000 I2S1...

Page 1208: ...on Bit Symbol Description Reset value 31 0 I2SRXFIFO 8 x 32 bit receive FIFO 0 Table 1005 I2S Status Feedback register STATE address 0x400A 2010 I2S0 and 0x400A 3010 I2S1 bit description Bit Symbol De...

Page 1209: ...s 0x400A 2014 I2S0 and 0x400A 3014 I2S1 bit description Bit Symbol Description Reset value 0 RX_DMA1_ENABLE When 1 enables DMA1 for I2S receive 0 1 TX_DMA1_ENABLE When 1 enables DMA1 for I2S transmit...

Page 1210: ...quation for the fractional rate generator is I2S_TX_MCLK PCLK X Y 2 Note If the value of X or Y is 0 then no clock is generated Also the value of Y must be greater than or equal to X 15 12 Reserved us...

Page 1211: ...rate for the I2S receiver is determined by the values in the RXRATE register The required RXRATE setting depends on the peripheral clock rate PCLK_I2S CLK_APB1_I2S and the desired MCLK rate such as 25...

Page 1212: ...it Symbol Description Reset value 7 0 Y_DIVIDER I2S receive MCLK rate denominator This value is used to divide PCLK to produce the receive MCLK Eight bits of fractional divide supports a wide range of...

Page 1213: ...etween I2S transmit and receive blocks When 1 enables 4 pin mode 0 3 TXMCENA Enable for the TX_MCLK output When 0 output of TX_MCLK is not enabled When 1 output of TX_MCLK is enabled 0 31 4 Reserved u...

Page 1214: ...word is considered to contain one 32 bit data word When switching between different word widths or different modes the I2S interface must be reset via the reset bit in the control register in order t...

Page 1215: ...onductors UM10503 Chapter 44 LPC43xx LPC43Sxx I2S interface CREG6 bits 12 and 13 select PLL0AUDIO for the I2S0 interface CREG bits 14 and 15 select BASE_AUDIO_CLK for the I2S1 interface Fig 147 I2S cl...

Page 1216: ...de See Figure 148 The I2S transmit function operates as a master The transmit clock source TX_MCLK is derived from PCLK using the fractional divider The WS used is the internally generated TX_WS The T...

Page 1217: ...TX_MCLK is derived from PCLK using the fractional divider The WS used is the internally generated TX_WS The TX_MCLK pin is enabled for output Bold lines indicate the clock path for this configuration...

Page 1218: ...receiver reference clock RX_MCLK The I2S transmit function operates as a master The transmit clock source is RX_MCLK The WS used is the internally generated TX_WS The TX_MCLK pin is not enabled for ou...

Page 1219: ...it clock source TX_SCK is provided by the external master on the TX_SCK pin The transmit bit rate divider must be set to 1 TXBITRATE 5 0 000000 for this mode to operate correctly The WS signal is prov...

Page 1220: ...ve to the receive function The receive function can operate in either master or slave mode determining the operating mode of the entire I2S interface The transmit clock source is RX_SCK The WS used is...

Page 1221: ...ce TX_MCLK is derived from the BASE_AUDIO_CLK The WS used is the internally generated TX_WS The TX_MCLK pin is enabled for output Bold lines indicate the clock path for this configuration CREG6 bits 1...

Page 1222: ...is provided by the external master on the TX_MCLK pin The WS used is the internally generated TX_WS The TX_MCLK pin is enabled for input Bold lines indicate the clock path for this configuration CREG...

Page 1223: ...er mode The I2S receive function operates as a master The receive clock source RX_MCLK is derived from PCLK using the fractional divider The WS used is the internally generated RX_WS The RX_MCLK pin i...

Page 1224: ...LK is derived from PCLK using the fractional divider The WS used is the internally generated RX_WS The RX_MCLK pin is enabled for output Bold lines indicate the clock path for this configuration CREG6...

Page 1225: ...ansmitter reference clock TX_MCLK The I2S receive function operates as a master The receive clock source is TX_MCLK The WS used is the internally generated RX_WS The RX_MCLK pin is not enabled for out...

Page 1226: ...clock source RX_SCK is provided by the external master on the RX_SCK pin The receive bit rate divider must be set to 1 RXBITRATE 5 0 000000 for this mode to operate correctly The WS signal is provided...

Page 1227: ...ve to the transmit function The transmit function can operate in either master or slave mode determining the operating mode of the entire I2S interface The receive clock source is TX_SCK The WS used i...

Page 1228: ...X_MCLK is derived from the BASE_AUDIO_CLK The WS used is the internally generated RX_WS The RX_MCLK pin is enabled for output Bold lines indicate the clock path for this configuration CREG6 bits 12 an...

Page 1229: ...mode External MCLK CREG bit 13 DAI bit 5 RXMODE bits 3 0 Description 0 0 0 0 0 1 Receiver master mode The I2S receive function operates as a master The receive clock source RX_MCLK is provided by the...

Page 1230: ...tx_depth_dma1 tx_level dmareq_rx_1 rx_depth_dma1 rx_level dmareq_tx_2 tx_depth_dma2 tx_level dmareq_rx_2 rx_depth_dma2 rx_level irq_tx tx_depth_irq tx_level irq_rx rx_depth_irq rx_level Table 1030 DM...

Page 1231: ...ctors UM10503 Chapter 44 LPC43xx LPC43Sxx I2S interface Fig 162 FIFO contents for various I2S modes LEFT 1 7 0 RIGHT 1 7 0 LEFT 7 0 RIGHT 7 0 Stereo 8 bit data mode N 3 7 0 N 2 7 0 N 1 7 0 N 7 0 Mono...

Page 1232: ...Section 45 7 5 2 for calculating the CAN bit rate Remark The clocks to the C_CAN0 and C_CAN1 interfaces can be set independently of each other Remark Use of C_CAN controller excludes operation of all...

Page 1233: ...iplex wiring by supporting distributed real time control with a very high level of security The CAN controller consists of a CAN core message RAM a message handler control registers and the APB interf...

Page 1234: ...2015 All rights reserved User manual Rev 2 1 10 December 2015 1234 of 1441 NXP Semiconductors UM10503 Chapter 45 LPC43xx LPC43Sxx C_CAN 45 5 Pin description Table 1033 C_CAN pin description Pin functi...

Page 1235: ...prescaler extension register 0x0000 Table 1042 0x01C Reserved IF1_CMDREQ R W 0x020 Message interface 1 command request 0x0001 Table 1045 IF1_CMDMSK_W R W 0x024 Message interface 1 command mask write d...

Page 1236: ...ble 1073 IR2 RO 0x144 Interrupt pending 2 0x0000 Table 1074 0x148 0x15C Reserved MSGV1 RO 0x160 Message valid 1 0x0000 Table 1075 MSGV2 RO 0x164 Message valid 2 0x0000 Table 1076 0x168 0x17C Reserved...

Page 1237: ...R R W 0x084 Message interface 2 command mask read direction 0x0000 Table 1050 IF2_MSK1 R W 0x088 Message interface 2 mask 1 0xFFFF Table 1052 IF2_MSK2 R W 0x08C Message interface 2 mask 2 0xFFFF Table...

Page 1238: ...ters CNTL address 0x400E 2000 C_CAN0 and 0x400A 4000 C_CAN1 bit description Bit Symbol Value Description Reset value Access 0 INIT Initialization 1 R W 0 Normal operation 1 Initialization is started O...

Page 1239: ...busoff recovery sequence the Error Management Counters will be reset During the waiting time after the resetting of INIT each time a sequence of 11 HIGH recessive bits has been monitored a Bit0Error c...

Page 1240: ...bit of logical value 1 but the monitored bus value was LOW dominant 0x5 Bit0Error During the transmission of a message or acknowledge bit or active error flag or overload flag the device wanted to se...

Page 1241: ...0 specification 6 EWARN Warning status 0 RO 0 Both error counters are below the error warning limit of 96 1 At least one of the error counters in the EC has reached the error warning limit of 96 7 BOF...

Page 1242: ...highest priority Among the message interrupts the Message Object s interrupt priority decreases with increasing message number A message interrupt is cleared by clearing the Message Object s INTPND bi...

Page 1243: ...X buffer 3 SILENT Silent mode 0 R W 0 Normal operation 1 The module is in silent mode 4 LBACK Loop back mode 0 R W 0 Loop back mode is disabled 1 Loop back mode is enabled 6 5 TX1_0 Control of TD pins...

Page 1244: ...sfer from the Message RAM allowing both processes to be interrupted by each other Each set of interface registers consists of message buffer registers controlled by their own command registers The com...

Page 1245: ...automatically set to 1 and the signal CAN_WAIT_B is pulled LOW to notify the CPU that a transfer is in progress After a wait time of 3 to 6 CAN_CLK periods the transfer between the Interface Register...

Page 1246: ...M is selected for data transfer 0x00 Not a valid message number This value is interpreted as 0x20 1 0x21 to 0x3F Not a valid message number This value is interpreted as 0x01 0x1F 1 0x01 R W 14 6 Reser...

Page 1247: ...47 CAN message interface command mask registers write direction IF1_CMDMSK_W address 0x400E 2024 C_CAN0 and 0x400A 4024 C_CAN1 bit description Bit Symbol Value Description Reset value Access 0 DATA_B...

Page 1248: ...a bytes 4 7 unchanged 1 Transfer data bytes 4 7 to message object 1 DATA_A Access data bytes 0 3 0 R W 0 Data bytes 0 3 unchanged 1 Transfer data bytes 0 3 to message object 2 TXRQST Access transmissi...

Page 1249: ...bytes 4 7 unchanged 1 Transfer data bytes 4 7 to IFx message buffer register 1 DATA_A Access data bytes 0 3 0 R W 0 data bytes 0 3 unchanged 1 Transfer data bytes 0 3 to IFx message buffer 2 NEWDAT A...

Page 1250: ...ion Reset value Access 0 DATA_B Access data bytes 4 7 0 R W 0 data bytes 4 7 unchanged 1 Transfer data bytes 4 7 to IFx message buffer register 1 DATA_A Access data bytes 0 3 0 R W 0 data bytes 0 3 un...

Page 1251: ...1 8 reserved 0 Table 1050 CAN message interface command mask registers read direction IF2_CMDMSK_R address 0x400E 2084 C_CAN0 and 0x400A 4084 C_CAN1 bit description continued Bit Symbol Value Descript...

Page 1252: ...e direction bit DIR is used for acceptance filtering 15 MXTD Mask extend identifier 1 R W 0 The extended identifier bit IDE has no effect on acceptance filtering 1 The extended identifier bit IDE is u...

Page 1253: ...ess 15 0 ID15_0 Message identifier 29 bit identifier extended frame 11 bit identifier standard frame 0x00 R W 31 16 Reserved 0 Table 1057 CAN message interface command arbitration 2 registers IF1_ARB2...

Page 1254: ...94 C_CAN0 and 0x400A 4094 C_CAN1 bit description Bit Symbol Value Description Reset value Access 12 0 ID28_16 Message identifier 29 bit identifier extended frame 11 bit identifier standard frame 0x00...

Page 1255: ...n continued Bit Symbol Value Description Reset value Access Table 1059 CAN message interface message control registers IF1_MCTRL address 0x400E 2038 C_CAN0 and 0x400A 4038 C_CAN1 bit description Bit S...

Page 1256: ...filtering 13 INTPND Interrupt pending 0 R W 0 This message object is not the source of an interrupt 1 This message object is the source of an interrupt The Interrupt Identifier in the Interrupt Regis...

Page 1257: ...gs to a FIFO buffer and is not the last message object of that FIFO buffer 1 Single message object or last message object of a FIFO buffer 8 TXRQST Transmit request 0 R W 0 This message object is not...

Page 1258: ...he source of an interrupt The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority 14 MSGLST Message lost only va...

Page 1259: ...8 DATA3 Data byte 3 0x00 R W 31 16 Reserved Table 1064 CAN message interface data A2 registers IF2_DA2 address 0x400E 20A0 C_CAN0 and 0x400A 40A0 C_CAN1 bit description Bit Symbol Description Reset v...

Page 1260: ...h Message Object a Transmission Request is pending The TXRQST bit of a specific Message Object can be set reset by the CPU via the IFx Message Interface Registers or by the Message Handler after recep...

Page 1261: ...e objects 16 to 1 By reading out the INTPND bits the CPU can check for which Message Object an interrupt is pending The INTPND bit of a specific Message Object can be set reset by the CPU via the IFx...

Page 1262: ...s 32 to 17 By reading out the MSGVAL bits the CPU can check which Message Object is valid The MSGVAL bit of a specific Message Object can be set reset by the CPU via the IFx Message Interface Register...

Page 1263: ...are reset After power on the contents of the message RAM is undefined 45 7 2 C_CAN operating modes 45 7 2 1 Software initialization The software initialization is started by setting the bit INIT in th...

Page 1264: ...ge Object during normal operation the CPU has to start by setting the MSGVAL bit to not valid When the configuration is completed MSAGVALis set to valid again 45 7 2 2 CAN message transfer Once the CA...

Page 1265: ...its TXRQST and NEWDAT in the Control Registers of the Message Buffers When a transmission starts bit TXRQST of the respective Message Buffer is reset while bit NEWDAT remains set When the transmission...

Page 1266: ...pled in the acknowledge slot of a data remote frame in Loop back mode In this mode the CAN core performs an internal feedback from its CAN_TD output to its CAN_RD input The actual value of the CAN_RD...

Page 1267: ...ed If the CPU has reset the BUSY bit a possible retransmission in case of lost arbitration or in case of an error is disabled The IF2 Registers are used as Receive Buffer After the reception of a mess...

Page 1268: ...1 6 Remark The three test functions for pin CAN_TD interfere with all CAN protocol functions The CAN_TD pin must be left in its default function when CAN message transfer or any of the test modes Loo...

Page 1269: ...er is cleared the CAN Protocol Controller state machine of the CAN core and the Message Handler State Machine control the CAN controller s internal data flow Received messages that pass the acceptance...

Page 1270: ...CAN Core cell is ready for loading and if there is no data transfer between the IFx Registers and Message RAM the MSGVAL bits in the Message Valid Register TXRQST bits in the Transmission Request Regi...

Page 1271: ...a Remote Frame while the requested Data Frame has just been received 45 7 3 4 2 Reception of a remote frame When a Remote Frame is received three different configurations of the matching Message Obje...

Page 1272: ...ace registers Neither MSGVAL nor TXRQST have to be reset before the update Even if only a part of the data bytes are to be updated all four bytes of the corresponding IFx Data A Register or IFx Data B...

Page 1273: ...e via the IFx Interface registers The data consistency is guaranteed by the Message Handler state machine To transfer the entire received message from message RAM into the message buffer software must...

Page 1274: ...stored into a Message Object of this FIFO Buffer starting with the Message Object with the lowest message number When a message is stored into a Message Object of a FIFO Buffer the NEWDAT bit of this...

Page 1275: ...nding interrupt with the highest priority disregarding their chronological order An interrupt remains pending until the CPU has cleared it Fig 169 Reading a message from the FIFO buffer to the message...

Page 1276: ...f the Message Objects where INTID points to the pending message interrupt with the highest interrupt priority The CPU controls whether a change of the Status Register may cause an interrupt bits EIE a...

Page 1277: ...e Baud Rate Prescaler BRP tq BRP fsys The C_CAN s system clock fsys is the frequency C_CAN peripheral clock The Synchronization Segment Sync_Seg is the part of the bit time where edges of the CAN bus...

Page 1278: ...re 170 and Table 1080 the bit rate and sample point can be expressed as follows using tq BRP CAN_CLK Bit rate 1 tq x total number of quantas 1 tq x 1 PROP_SEG TSEG1 TSEG2 CAN_CLK BRP x 1 PROP_SEG TSEG...

Page 1279: ...ed as Master Slave or Master Slave Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus Programmable clock allows adjustment of I2C transfer...

Page 1280: ...nsmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other...

Page 1281: ...1000 Name Access Address offset Description Reset value 1 Reference CONSET R W 0x000 I2C Control Set Register When a one is written to a bit of this register the corresponding bit in the I2C control...

Page 1282: ...r operation of the I2C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address 0x00 Table 1093 DATA_BUFFER RO 0...

Page 1283: ...LH together determine the clock frequency generated by an I2C master and certain times used in slave mode 0x04 Table 1090 CONCLR WO 0x018 I2C Control Clear Register When a one is written to a bit of t...

Page 1284: ...er master mode and transmit a START condition or transmit a Repeated START condition if it is already in master mode MASK1 R W 0x034 I2C Slave address mask register 1 This mask register is associated...

Page 1285: ...cts the STOP condition STO is cleared automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as...

Page 1286: ...ved data is located at the MSB of DAT 46 7 4 I2C Slave Address register 0 This register is readable and writable and are only used when an I2C interface is set to slave mode In master mode this regist...

Page 1287: ...nd SCLH values SCLL and SCLH values should not necessarily be the same Software can set different duty cycles on SCL by setting these two registers For example the I2C bus specification defines the SC...

Page 1288: ...T register Writing 0 has no effect I2ENC is the I2C Interface Disable bit Writing a 1 to this bit clears the I2EN bit in the CONSET register Writing 0 has no effect 46 7 7 I2C Monitor mode control reg...

Page 1289: ...ode disabled 1 The I2C module will enter monitor mode In this mode the SDA output will be forced high This will prevent the I2C module from outputting data of any kind including ACK onto the I2C data...

Page 1290: ...General Call bit When this bit is set the General Call address 0x00 is recognized All four registers including ADR0 see Table 1088 will be cleared to this disabled state on reset You should program t...

Page 1291: ...ectly as usual and the behavior of DAT will not be altered in any way Although the DATA_BUFFER register is primarily intended for use in monitor mode with the ENA_SCL bit 0 it will be available for re...

Page 1292: ...to the SIC bit in the CONCLR register The STA bit should be cleared after writing the slave address The first byte transmitted contains the slave address of the receiving device 7 bits and the data d...

Page 1293: ...e must load the slave address and the data direction bit to the I2C Data register DAT and then clear the SI bit In this case the data direction bit R W should be 1 to indicate a read When the slave ad...

Page 1294: ...rection bit If the direction bit is 0 W it enters slave receiver mode If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is...

Page 1295: ...rdware looks for its own slave address and the General Call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardwa...

Page 1296: ...special pad designed to conform to the I2C specification Fig 177 I2C serial interface block diagram APB BUS STATUS REGISTER I2CnSTAT CONTROL REGISTER and SCL DUTY CYLE REGISTERS I2CnCONSET I2CnCONCLR...

Page 1297: ...first received 8 bit byte with the General Call address 0x00 If an equality is found the appropriate status bits are set and an interrupt is requested 46 9 5 Shift register DAT This 8 bit register co...

Page 1298: ...mmable clock pulse generator provides the SCL clock pulses when the I2C block is in the master transmitter or master receiver mode It is switched off when the I2C block is in slave mode The I2C output...

Page 1299: ...that correspond to ones in the value written Conversely writing to CONCLR will clear bits in the I2C control register that correspond to ones in the value written 46 9 10 Status decoder and status reg...

Page 1300: ...ables from Table 1101 to Table 1107 46 10 1 Master Transmitter mode In the master transmitter mode a number of data bytes are transmitted to a slave receiver see Figure 180 Before the master transmitt...

Page 1301: ...used by the interrupt service routine to enter the appropriate state service routine that loads DAT with the slave address and the data direction bit SLA W The SI bit in CON must then be reset before...

Page 1302: ...en received Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will be received No DAT action or 1 0 0 X Repeated START will be transmitted No DAT action or 0 1 0 X STOP condition will be...

Page 1303: ...OR A A OR A A other Master continues other Master continues A other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Data byte Not Acknowledge received...

Page 1304: ...routine must load DAT with the 7 bit slave address and the data direction bit SLA R The SI bit in CON must then be cleared before the serial transfer can continue When the slave address and the data...

Page 1305: ...when the bus becomes free 0x40 SLA R has been transmitted ACK has been received No DAT action or 0 0 0 0 Data byte will be received NOT ACK bit will be returned No DAT action 0 0 0 1 Data byte will be...

Page 1306: ...A S W A A OR A A P other Master continues other Master continues A other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Acknowledge bit Not Acknowledge recei...

Page 1307: ...by its own slave address followed by the data direction bit which must be 0 W for the I2C block to operate in the slave receiver mode After its own slave address and the W bit have been received the s...

Page 1308: ...urned No DAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No DAT action X 0 0 1 Data byte will be received and ACK will be returned 0x80 Previously addressed with own SLV...

Page 1309: ...l call address will be recognized if ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or Repeated START condition has been received while still addre...

Page 1310: ...ne or more Data bytes arbitration lost as Master and addressed as Slave last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave by General Call reception of the o...

Page 1311: ...is set and a valid status code can be read from STAT This status code is used to vector to a state service routine and the appropriate action to be taken for each of these status codes is detailed in...

Page 1312: ...tted NOT ACK has been received No DAT action or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No DAT action or 0 0 0 1 Switched to not addressed SLV mode...

Page 1313: ...used when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge...

Page 1314: ...epeated START condition see Figure 184 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the I2C hardware detects a Repeated START condition...

Page 1315: ...ossible for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a temporary short circuit between SDA and SC...

Page 1316: ...nchronization so a START should be generated to insure that all I2C peripherals are synchronized 46 10 6 5 Bus error A bus error occurs when a START or STOP condition is detected at an illegal positio...

Page 1317: ...ion 46 10 9 I2C interrupt service When the I2C interrupt is entered STAT contains a status code which identifies one of the 26 state services to be executed 46 10 10 The state service routines Each st...

Page 1318: ...er Receive buffer 5 Initialize the Master data counter to match the length of the message to be received 6 Exit 46 11 4 I2C interrupt routine Determine the I2C state and which state routine will be us...

Page 1319: ...e 8 or State 10 Slave Address Write has been transmitted ACK has been received The first data byte will be transmitted an ACK bit will be received 1 Load DAT with first data byte from Master Transmit...

Page 1320: ...to CONSET to set the STA and AA bits 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 46 11 7 Master Receive states 46 11 7 1 State 0x40 Previous state was State 08 or State 10 Slave Address Read h...

Page 1321: ...ddress Write has been received ACK has been returned Data will be received and ACK returned 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Set up Slave Receive...

Page 1322: ...returned Additional data will be read 1 Read data byte from DAT into the Slave Receive buffer 2 Decrement the Slave data counter skip to step 5 if not the last data byte 3 Write 0x0C to CONCLR to clea...

Page 1323: ...Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received 1 Load DAT from Slave Transmit buffer with first data byte 2 Write 0x04 to CONSET to s...

Page 1324: ...to CONCLR to clear the SI flag 4 Increment Slave Transmit buffer pointer 5 Exit 46 11 9 4 State 0xC0 Data has been transmitted NOT ACK has been received Not addressed Slave mode is entered 1 Write 0x0...

Page 1325: ...mber 2015 User manual Table 1108 10 bit ADC0 1 channels for different packages on parts LPC4370 with 12 bit ADCHS Pin LBGA256 TFBGA100 Notes P4_3 yes Channel 0 ADC0 P4_1 yes Channel 1 ADC0 PF_8 yes Ch...

Page 1326: ...ADC0 and channel 5 ADC1 PB_6 yes yes Channel 6 ADC0 and channel 6 ADC1 PC_3 yes yes Channel 0 ADC0 and channel 0 ADC1 and DAC PC_0 yes yes yes Channel 1 ADC0 and channel 1 ADC1 PF_9 yes yes Channel 2...

Page 1327: ...ltiple inputs Optional conversion on transition on input pin or Timer Match signal Individual result registers for each A D channel to reduce interrupt overhead Connected to bandgap reference see Sect...

Page 1328: ...ddress 0x400E 3000 Name Access Address offset Description Reset value 1 Reference CR R W 0x000 A D Control Register The AD0CR register must be written to select the operating mode before A D conversio...

Page 1329: ...0x00C A D Interrupt Enable Register This register contains enable bits that allow the DONE flag of each A D channel to be included or excluded from contributing to the generation of an A D interrupt...

Page 1330: ...urce a slower clock may be desirable 0 16 BURST Controls Burst mode 0 0 Conversions are software controlled and require 11 clocks 1 The AD converter does repeated conversions at the rate selected by t...

Page 1331: ...start3 0x5 Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input ADC start4 0x6 Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 ADC start5 0x7...

Page 1332: ...en If the AD0 1CR is written while a conversion is still in progress this bit is set and a new conversion is started 0 Table 1115 A D Global Data register GDR address 0x400E 3004 ADC0 and 0x400E 4004...

Page 1333: ...e ADSTAT register is 1 The ADINT bit is one when any of the DONE bits of the A D channels which are enabled for interrupts via the ADINTEN register are one Software can use the Interrupt Enable bit in...

Page 1334: ...for generating an interrupt A pending DMA request is cleared after the DMA has read from the requesting channel s A D data register DR 7 0 Reading from the global data register GDR does not clear any...

Page 1335: ...t 48 3 Basic configuration The ADCHS is configured as follows See Table 1119 for clocking and power control The ADCHS is reset by the ADCHS_RST reset 60 The ADCHS interrupt is connected to interrupt s...

Page 1336: ...equence is defined by two descriptor tables see Table 1137 and Table 1138 The tables can be loaded by general purpose DMA or software Remark When sampling long sequences that do not fit in the FIFO th...

Page 1337: ...Q R W 0x0004 Set or clear DMA write request 0x00000001 Table 1123 FIFO_STS RO 0x0008 Indicates FIFO fill level status 0x00000000 Table 1124 FIFO_CFG R W 0x000C Configures FIFO fill level that triggers...

Page 1338: ...e 1137 DESCRIPTOR1_0 to DESCRIPTOR1_7 R W 0x0320 to 0x033C Table 1 descriptors n n 0 to 7 0x000090E0 Table 1138 CLR_EN0 WO 0x0F00 Interrupt 0 clear mask 0x00000000 Table 1139 SET_EN0 WO 0x0F04 Interru...

Page 1339: ...anual Rev 2 1 10 December 2015 1339 of 1441 NXP Semiconductors UM10503 Chapter 48 12 bit ADC ADCHS Table 1123 DMA request register DMA_REQ address 0x400F 0004 bit description Bit Symbol Description Re...

Page 1340: ...s register also defines at what FIFO fill level the interrupt flag FIFO_FULL is asserted Remark The channel ID is optional This is configured in register CONFIG Table 1124 FIFO fill level register FIF...

Page 1341: ...external signal should be synchronized Synchronization is needed for short duration trigger inputs Synchronization introduces a latency of 2 3 ADC clock cycles When synchronization is set here then it...

Page 1342: ...to be set to 0b10 This result will also generate an interrupt 1 request if enabled to do so via the SET_EN1 bits associated with the comparator THCMP_ARANGE bits in the SET_EN1 register If for two su...

Page 1343: ...address 0x400F 0024 bit description Bit Symbol Description Reset value 11 0 THR_LOW_B Low Compare Threshold Register B Contains the lower threshold level for automatic threshold comparison for any cha...

Page 1344: ...ts DC coupled For AC coupling the DC biasing is generated internally by setting DCINNEG 1 and DCINPOS 1 5 4 THCMP_CROSS Threshold Crossing Comparison result 00 No Threshold Crossing detected 01 Downwa...

Page 1345: ...r These registers access the output FIFO that contains the 12 bit ADC conversion results All registers remap to the FIFO output It is remapped 16 times to allow for DMA access reading at 16 consecutiv...

Page 1346: ...LE register and the mask bit associated with DSCR_DONE is set by register SET_EN0 When POWER_DOWN is set the ADC is powered down after the conversion has finished The ADC is automatically woken up bef...

Page 1347: ...1 When writing new table entries to DESCRIPTOR0 these registers read do not reflect the table used by the ADC processing until UPDATE_TABLE has been set 1 again Table 1137 Descriptor table 0 registers...

Page 1348: ...Symbol Description Reset value Table 1138 Descriptor table 1 registers DESCRIPTOR1_ 0 7 address 0x400F 0320 DESCRIPTOR1_0 to 0x400F 033C DESCRIPTOR1_7 bit description Bit Symbol Description Reset val...

Page 1349: ...descriptors of this table Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set This field is write only A re...

Page 1350: ...IFO is empty 0x1 2 FIFO_OVERFLOW FIFO was full conversion sample is not stored and lost 0x0 3 DSCR_DONE The descriptor INTERRUPT field was enabled and its sample is converted 0x0 4 DSCR_ERROR The ADC...

Page 1351: ...nable 0x00000000 31 30 Reserved Table 1148 Interrupt 1 status register STATUS1 address 0x400F 0F2C bit description Bit Symbol Description Reset value 0 THCMP_BRANGE0 Input channel 0 result below range...

Page 1352: ...ents of register LAST_SAMPLE 3 before it has been read 20 THCMP_BRANGE4 Input channel 4 result below range 21 THCMP_ARANGE4 Input channel 4 result above range 22 THCMP_DCROSS4 Input channel 4 result d...

Page 1353: ...used then the ADC can be used in true differential mode When sampling different channels in a high speed interleaved fashion some crosstalk may occur when one input is immediately sampled after anothe...

Page 1354: ...fering usage one table is active while the other table can be preloaded and swapped with the active table to become the new active table The sampling time instance is defined by a 14 bit descriptor ti...

Page 1355: ...bles are double buffered one active table and one shadow table The shadow table can be accessed by software via registers DESCRIPTOR_0 or DESCRIPTOR_1 or loaded via DMA see Section 48 7 4 2 The shadow...

Page 1356: ...scriptor related interrupt is raised under the following conditions see also Section 48 6 19 when a descriptor entry with the descriptor INTERRUPT field set has been processed when a sample was conver...

Page 1357: ...channel in the SET_EN1 register 48 7 5 3 FIFO status interrupts An Interrupt can be raised at a defined FIFO level See Section 48 6 19 48 7 6 ADC external triggers Conversions on the 12 bit ADC can b...

Page 1358: ...t is connected to interrupt slot 0 in the NVIC For connecting to the GPDMA use the DMAMUX register Table 101 in the CREG block and enable the GPDMA channel in the DMA Channel Configuration registers S...

Page 1359: ...s a voltage reference level VREF for the D A converter VSSA Ground Table 1153 Register overview DAC base address 0x400E 1000 Name Access Address offset Description Reset value Reference CR R W 0x000 D...

Page 1360: ...0 0 This bit is cleared on any write to the DAC CR register 1 This bit is set by hardware when the timer times out 1 DBLBUF_ENA DMA double buffering 0 0 Disable double buffering 1 Enable double buffer...

Page 1361: ...set in DAC CTRL In this case any write to the DAC CR register will only load the pre buffer which shares its register address with the DAC CR register The DAC CR itself will be loaded from the pre bu...

Page 1362: ...ogram time Endurance of 100 k erase program cycles 50 4 General description The EEPROM can be read and written erased A write operation involves two steps The first step is writing a minimum of 1 word...

Page 1363: ...d register 0 Table 1159 RWSTATE R W 0x008 EEPROM read wait state register 0x0000 0E07 Table 1160 AUTOPROG R W 0x00C EEPROM auto programming register 0 Table 1161 WSTATE R W 0x010 EEPROM wait state reg...

Page 1364: ...ppropriate values in this wait state register for EEPROM operation The fields are 1 encoded so programming zero will result in a one cycle wait state The register contains two fields each representing...

Page 1365: ...The delays for the write and erase program operations are combined to simplify the software interface Timing for write and erase program operations is almost identical Table 1161 EEPROM auto programmi...

Page 1366: ...6 EEPROM power down register Use the EEPROM power down register to put the EEPROM device in power down mode Do not put the EEPROM in power down mode during a pending EEPROM operation After clearing th...

Page 1367: ...d value is undefined only zero should be written NA Table 1166 Interrupt enable set register INTENSET address 0x4000 EFDC bit description Bits Symbol Description Reset value 1 0 Reserved Read value is...

Page 1368: ...g bit of the INTENCLR register 0 31 3 Reserved The value read from a reserved bit is not defined NA Table 1169 Interrupt status clear register INTSTATCLR address 0x4000 EFE8 bit description Bits Symbo...

Page 1369: ...begins at EEPROM_START 256 etc Writes to a page cannot cross a 128 page boundary Remark Before reading this data from the EEPROM or writing to another page program the contents of the page register in...

Page 1370: ...ding with 1111100 automatically starts the erase program cycle This mode is useful to store multiple full pages of data During programming the EEPROM is not available for other operations To prevent u...

Page 1371: ...ction 6 6 Code Read Protection CRP or use the CREG5 register Section 11 4 4 CREG5 control register 51 3 Features ARM Cortex M4 Supports both standard JTAG and ARM Serial Wire Debug modes Direct debug...

Page 1372: ...CREG block see Section 11 4 8 Remark The ETM time stamping feature is not implemented 51 5 Pin description Table 1171 to Table 1173 indicate the various pin functions related to debug and trace Some...

Page 1373: ...ire and JTAG interface modes in a 20 pin 0 1 connector It can be used to access all SWD SWV and JTAG signals Table 1172 Serial Wire Debug pin description 1 Pin Name Type Description SWDCLK Input Seria...

Page 1374: ...connector The 10 pin Cortex debug connector can access to all SWD SWV and JTAG signals 51 6 3 Cortex Debug ETM connector 20 pin If the debug trace feature will be used there is also a debug with trac...

Page 1375: ...2 1 10 December 2015 1375 of 1441 NXP Semiconductors UM10503 Chapter 51 LPC43xx LPC43Sxx JTAG Serial Wire Debug SWD and Fig 194 Cortex Debug ETM Connector 3 3 V 3 3 V Key 1 3 5 7 9 11 13 15 17 19 2 4...

Page 1376: ...as single stepping Debugging is disabled if code read protection of the flash memory is enabled 51 8 Debug memory re mapping Following chip reset a portion of the Boot ROM is mapped to address 0 so th...

Page 1377: ...gger can debug the ARM Cortex M4 and the ARM Cortex M0 cores separately or both cores simultaneously Remark In order to debug the ARM Cortex M0 release the M0 reset by software in the RGU block Remark...

Page 1378: ...to speculate the address early B The number of cycles required to perform the barrier operation For DSB and DMB the minimum number of cycles is zero For ISB the minimum number of cycles is equivalent...

Page 1379: ...UDIV Rd Rn Rm 2 to 12 1 Saturate Signed SSAT Rd imm op2 1 Unsigned USAT Rd imm op2 1 Compare Compare CMP Rn op2 1 Negative CMN Rn op2 1 Logical AND AND Rd Rn op2 1 Exclusive OR EOR Rd Rn op2 1 OR ORR...

Page 1380: ...including PC LDM Rn reglist PC 1 N P Store Word STR Rd Rn op2 2 2 Halfword STRH Rd Rn op2 2 2 Byte STRB Rd Rn op2 2 2 Signed halfword STRSH Rd Rn op2 2 2 Signed byte STRSB Rd Rn op2 2 2 User word STRT...

Page 1381: ...non zero CBNZ Rn label 1 or 1 P 3 Byte table branch TBB Rn Rm 2 P Halfword table branch TBH Rn Rm LSL 1 2 P State change Supervisor call SVC imm If then else IT cond 1 4 Disable interrupts CPSID flags...

Page 1382: ...signed multiply with 64 bit accumulate top by bottom SMLALTB 1 16 bit signed multiply with 64 bit accumulate top by top SMLALTT 1 16 bit signed multiply yielding 32 bit result bottom by bottom SMULBB...

Page 1383: ...ted 8 bit to 16 bit signed addition SXTAB16 1 Extracted 16 bit to 32 bit signed addition SXTAH 1 Miscellaneous Data Processing Select bytes based on GE bits SEL 1 Unsigned sum of quad 8 bit unsigned a...

Page 1384: ...ing dual 16 bit unsigned subtract USUB16 1 GE setting quad 8 bit unsigned subtract USUB8 1 Parallel Addition and Subtraction Dual 16 bit unsigned saturating addition and subtraction with exchange UQAS...

Page 1385: ...ADD SP SP imm 1 From address from SP ADD Rd SP imm 1 From address from PC ADR Rd label 1 Subtract Lo and Lo SUBS Rd Rn Rm 1 3 bit immediate SUBS Rd Rn imm 1 8 bit immediate SUBS Rd Rd imm 1 With carry...

Page 1386: ...n imm 2 Byte immediate offset STRB Rd Rn imm 2 Word register offset STR Rd Rn Rm 2 Halfword register offset STRH Rd Rn Rm 2 Byte register offset STRB Rd Rn Rm 2 SP relative STR Rd SP imm 2 Multiple ST...

Page 1387: ...op list including PC and assumes load or store does not generate a HardFault exception 3 3 if taken 1 if not taken 4 Cycle count depends on core and debug configuration 5 Excludes time spend waiting f...

Page 1388: ...SECTOR_NOT_BLANK 0x00000009 ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION 0x0000000A ERR_ISP_COMPARE_ERROR 0x0000000B ERR_ISP_BUSY Flash programming hardware interface is busy 0x0000000C ERR_ISP_PAR...

Page 1389: ..._AES_DMA_MUX_CFG 0x00030006 SEC_AES_DMA_BUSY USB device stack related errors ERR_USBD_BASE 0x00040000 b 0x00040001 ERR_USBD_INVALID_REQ ERR_USBD_BASE 1 invalid request b 0x00040002 ERR_USBD_UNHANDLED...

Page 1390: ...070009 ERR_OTP_ILLEGAL_BANK CLK related errors ERR_CLK_BASE 0x000B0000 0x000B0001 ERR_CLK_NOT_IMPL ERR_CLK_BASE 1 0x000B0002 ERR_CLK_INVALID_PARAM 0x000B0003 ERR_CLK_INVALID_SLICE 0x000B0004 ERR_CLK_O...

Page 1391: ...on DAC Digital to Analog Converter DC DC Direct Current to Direct Current DMA Direct Memory Access FIPS Federal Information Processing Standard GPIO General Purpose Input Output IRC Internal RC IrDA I...

Page 1392: ...PC4350 30 20 10 flashless parts data sheet http www nxp com documents data_sheet LPC4350_30_20_10 pdf 4 LPC4370 flashless parts data sheet http www nxp com documents data_sheet LPC4370 pdf 5 LPC435x 3...

Page 1393: ...uctors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction o...

Page 1394: ...d 77 Table 39 ISP Read Memory command 77 Table 40 ISP Prepare sectors for write operation command 78 Table 41 ISP Copy command 79 Table 42 ISP Go command 80 Table 43 ISP Erase sector command 80 Table...

Page 1395: ...04 ETB SRAM configuration register ETBCFG address 0x4004 3128 bit description 151 Table 105 CREG6 control register CREG6 address 0x4004 312C bit description 152 Table 106 M4 TXEV clear register M4TXEV...

Page 1396: ...le 152 PLL0 for USB settings for 480 MHz output clock 206 Table 153 PLL0AUDIO divider settings for 12 MHz input 206 Table 154 PLL0AUDIO divider setting for 12 MHz with fractional divider bypassed 208...

Page 1397: ...NAIO1 register 426 Table 200 ADC1 function select register ENAIO1 address 0x4008 6C8C bit description 427 Table 201 Pins controlled by the ENAIO2 register 427 Table 202 Analog function select register...

Page 1398: ...it description 464 Table 248 Pin interrupt level rising edge interrupt enable register IENR address 0x4008 7004 bit description 464 Table 249 Pin interrupt level rising edge interrupt set register SIE...

Page 1399: ...0 bit description 490 Table 289 GPIO output control register GPIO_OUTREG address 0x4010 1214 bit description 490 Table 290 GPIO output enable register GPIO_OENREG address 0x4010 1218 bit description 4...

Page 1400: ...Interrupt Terminal Count Status Register RAWINTTCSTAT address 0x4000 2014 bit description 518 Table 339 DMA Raw Error Interrupt Status Register RAWINTERRSTAT address 0x4000 2018 bit description 518 Ta...

Page 1401: ...Register BUFADDR address 0x4000 4098 bit description 565 Table 391 SEND_AUTO_STOP bit 566 Table 392 CMD register settings for No Data Command572 Table 393 CMD register settings for Single block or Mu...

Page 1402: ...escription 618 Table 443 SDRAM mode register description 622 Table 444 SPIFI clocking and power control 627 Table 445 SPIFI flash memory map 628 Table 446 SPIFI pin description 628 Table 447 Register...

Page 1403: ...USB Endpoint Status register ENDPTSTAT address 0x4000 61B8 bit description 681 Table 499 USB Endpoint Complete register ENDPTCOMPLETE address 0x4000 61BC bit description 682 Table 500 USB Endpoint 0 C...

Page 1404: ...e register in host mode USBMODE_H address 0x4000 71A8 bit description 760 Table 556 USB Endpoint Setup Status register ENDPTSETUPSTAT address 0x4000 71AC bit description 761 Table 557 USB Endpoint Pri...

Page 1405: ...b second increment register SUBSECOND_INCR address 0x4001 0704 bit description 840 Table 621 System time seconds register SECONDS address 0x4001 0708 bit description 840 Table 622 System time nanoseco...

Page 1406: ...Table 679 LCD Control register CTRL address 0x4000 8018 bit description 916 Table 680 Interrupt Mask register INTMSK address 0x4000 801C bit description 918 Table 681 Raw Interrupt Status register INT...

Page 1407: ...bit 1 972 Table 738 SCT match reload registers 0 to 15 MATCHREL address 0x4000 0200 MATCHRELOAD0 to 0x4000 023C MATCHRELOAD15 bit description REGMODEn bit 0 972 Table 739 SCT capture control registers...

Page 1408: ...Table 784 Timer2 inputs and outputs 1021 Table 785 Timer3 inputs and outputs 1021 Table 786 Register overview Timer0 1 2 3 register base addresses 0x4008 4000 TIMER0 0x4008 5000 TIMER1 0x400C 3000 TIM...

Page 1409: ...ew QEI base address 0x400C 6000 1066 Table 828 QEI Control register CON address 0x400C 6000 bit description 1068 Table 829 QEI Interrupt Status register STAT address 0x400C 6004 bit description 1068 T...

Page 1410: ...87 Seconds register SEC address 0x4004 6020 bit description 1095 Table 888 Minutes register MIN address 0x4004 6024 bit description 1095 Table 889 Hours register HRS address 0x4004 6028 bit descriptio...

Page 1411: ...le 935 USART Scratch Pad Register SCR addresses 0x4008 101C USART0 0x400C 101C USART2 0x400C 201C USART3 bit description 1131 Table 936 Autobaud Control Register ACR addresses 0x4008 1020 USART0 0x400...

Page 1412: ...Clear register IMSC address 0x4008 3014 SSP0 0x400C 5014 SSP1 bit description 1179 Table 982 SSP Raw Interrupt Status register RIS address 0x4008 3018 SSP0 RIS 0x400C 5018 SSP1 bit description 1179 Ta...

Page 1413: ...C_CAN0 and 0x400A 4000 C_CAN1 bit description 1238 Table 1037 CAN status register STAT address 0x400E 2004 C_CAN0 and 0x400A 4004 C_CAN1 bit description 1240 Table 1038 CAN error counter EC address 0...

Page 1414: ...2 register TXREQ2 address 0x400E 2104 C_CAN0 and 0x400A 4104 C_CAN1 bit description 1260 Table 1071 CAN new data 1 register ND1 address 0x400E 2120 C_CAN0 and 0x400A 4120 C_CAN1 bit description 1261...

Page 1415: ...n 1340 Table 1125 FIFO configuration register FIFO_CFG address 0x400F 000C bit description 1340 Table 1126 Trigger register TRIGGER address 0x400F 0010 bit description 1341 Table 1127 Descriptor statu...

Page 1416: ...it state register WSTATE address 0x4000 E010 bit description 1365 Table 1163 EEPROM clock divider register CLKDIV address 0x4000 E014 bit description 1366 Table 1164 EEPROM power down DCM register PWR...

Page 1417: ...105 Fig 30 AES data encryption decryption 107 Fig 31 AES driver pointer structure 108 Fig 32 AES endianness 114 Fig 33 Event router block diagram 123 Fig 34 Power mode transitions 158 Fig 35 BASE_M4_...

Page 1418: ...chdog block diagram 1107 Fig 123 Early Watchdog Feed with Windowed Mode Enabled 1108 Fig 124 Correct Watchdog Feed with Windowed Mode Enabled 1108 Fig 125 Watchdog Warning Interrupt 1108 Fig 126 Event...

Page 1419: ...Fig 179 Serial clock synchronization 1298 Fig 180 Format and states in the Master Transmitter mode 1303 Fig 181 Format and states in the Master Receiver mode 1306 Fig 182 Format and states in the Sla...

Page 1420: ...rotection Unit MPU 37 3 4 Memory map flashless parts 38 3 5 Memory map parts with on chip flash 40 3 6 AHB Multilayer matrix configuration 43 Chapter 4 LPC43xx LPC43Sxx One Time Programmable OTP memor...

Page 1421: ...ke ISP 93 6 8 11 Erase page 93 6 8 12 Set active boot flash bank 93 6 9 ISP IAP Status Codes 94 6 10 JTAG flash programming interface 95 6 11 Flash signature generation 95 6 11 1 Register description...

Page 1422: ...12 LPC43xx LPC43Sxx Power Management Controller PMC 12 1 How to read this chapter 157 12 2 General description 157 12 2 1 Active mode 159 12 2 2 Sleep mode 159 12 2 3 Deep sleep mode 159 12 2 4 Power...

Page 1423: ...mode 204 Power down mode 204 13 8 Example CGU configurations 205 13 8 1 Programming the CGU for Deep sleep and Power down modes 205 13 8 2 Programming the CGU for using I2S at peripheral clock rate of...

Page 1424: ...ption 437 18 4 1 Timer 0 CAP0_0 capture input multiplexer CAP0_0_IN 439 18 4 2 Timer 0 CAP0_1 capture input multiplexer CAP0_1_IN 439 18 4 3 Timer 0 CAP0_2 capture input multiplexer CAP0_2_IN 440 18 4...

Page 1425: ...Recommended practices 475 Chapter 20 LPC43xx LPC43Sxx Serial GPIO SGPIO 20 1 How to read this chapter 476 20 2 Basic configuration 476 20 3 Features 476 20 4 General description 477 20 4 1 SGPIO to A...

Page 1426: ...Lock control 529 21 6 20 2 Flow control and transfer type 529 21 7 Functional description 530 21 7 1 DMA controller functional description 530 21 7 1 1 AHB slave interface 530 21 7 1 2 Control logic...

Page 1427: ...LOCK RW_BLK 581 22 7 5 2 4 Sending Command Completion Signal Disable 583 22 7 5 2 5 Recovery after Command Completion Signal Time out 583 22 7 5 2 6 Reduced ATA Command Set 583 22 7 5 3 Controller DMA...

Page 1428: ...IFI cache limit register 633 24 6 6 SPIFI data register 633 24 6 7 SPIFI memory command register 633 24 6 8 SPIFI status register 635 24 7 Functional description 635 24 7 1 Data transfer 635 24 7 2 So...

Page 1429: ...ion 693 25 9 Device data structures 693 25 9 1 Endpoint queue head dQH 694 25 9 1 1 Endpoint capabilities and characteristics descriptor fields 695 25 9 1 2 Current dTD pointer descriptor fields 696 2...

Page 1430: ...URSTSIZE 746 26 6 10 Transfer buffer Fill Tuning register TXFILLTUNING 747 26 6 10 1 Device controller 747 26 6 10 2 Host controller 747 26 6 11 USB ULPI viewport register ULPIVIEWPORT 748 26 6 12 BIN...

Page 1431: ...onds register 843 28 6 25 System time higher words seconds register 843 28 6 26 Time stamp status register 843 28 6 27 DMA Bus mode register 844 28 6 28 DMA Transmit poll demand register 846 28 6 29 D...

Page 1432: ...6 7 LCD Control register 916 29 6 8 Interrupt Mask register 918 29 6 9 Raw Interrupt Status register 918 29 6 10 Masked Interrupt Status register 919 29 6 11 Interrupt Clear register 919 29 6 12 Uppe...

Page 1433: ...without using states 984 Chapter 31 LPC43xx LPC43Sxx State Configurable Timer SCT with dither engine 31 1 How to read this chapter 985 31 2 Features 985 31 3 Register description 986 31 3 1 SCT confi...

Page 1434: ...PWM Interrupt Flags clear address 1056 33 7 12 MCPWM Capture clear address 1056 33 8 Functional description 1057 33 8 1 Pulse width modulation 1057 Edge aligned PWM without dead time 1057 Center align...

Page 1435: ...on 1090 37 6 1 Interrupt Location Register 1091 37 6 2 Clock Control Register 1091 37 6 3 Counter Increment Interrupt Register 1092 37 6 4 Alarm Mask Register 1092 37 6 5 Consolidated time registers 1...

Page 1436: ...USART RS485 Control register 1137 40 6 17 USART RS485 Address Match register 1138 40 6 18 USART RS485 Delay value register 1139 40 6 19 USART Synchronous mode control register 1139 40 6 20 USART Tran...

Page 1437: ...A 1 1185 42 7 3 National Semiconductor Microwire frame format 1186 42 7 3 1 Setup and hold time requirements on CS with respect to SK in Microwire mode 1187 Chapter 43 LPC43xx LPC43Sxx SPI 43 1 How to...

Page 1438: ...ters 1253 45 6 2 4 4 CAN message interface command arbitration 2 registers 1253 45 6 2 4 5 CAN message interface message control registers 1255 45 6 2 4 6 CAN message interface data A1 registers 1258...

Page 1439: ...ter Receiver mode 1304 46 10 3 Slave Receiver mode 1307 46 10 4 Slave Transmitter mode 1311 46 10 5 Miscellaneous states 1313 46 10 5 1 STAT 0xF8 1313 46 10 5 2 STAT 0x00 1313 46 10 6 Some special cas...

Page 1440: ...upt 1 status register 1351 48 6 26 Interrupt 1 clear status register 1352 48 6 27 Interrupt 1 set status register 1352 48 7 Functional description 1353 48 7 1 Analog inputs 1353 48 7 2 Reduced power m...

Page 1441: ...bedded Trace Macrocell ETM 1372 51 5 Pin description 1372 51 6 Debug connections 1373 51 6 1 ARM Standard JTAG connector 20 pin 1373 51 6 2 Cortex debug connector 10 pin 1374 51 6 3 Cortex Debug ETM c...

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