NXP Semiconductors LPC43Sxx, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 349 of 1441
NXP Semiconductors
UM10503
Chapter 16: LPC43xx/LPC43Sxx Pin configuration
[6] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if V
DD(IO)
present;
if V
DD(IO)
not present, do not exceed 3.3 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital
section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP
register.
[7] 5 V tolerant transparent analog pad.
[8] For maximum load C
L
= 6.5

F and maximum resistance R
pd
= 80 k

, the VBUS signal takes about 2 s to fall from VBUS = 5 V to VBUS
= 0.2 V when it is no longer driven.
[9] Transparent analog pad. Not 5 V tolerant.
[10] Pad provides USB functions (5 V tolerant if V
DD(IO)
present; if V
DD(IO)
not present, do not exceed 3.3 V). It is designed in accordance
with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
[11] Open-drain 5 V tolerant digital I/O pad, compatible with I
2
C-bus Fast Mode Plus specification. This pad requires an external pull-up to
provide output functionality. When power is switched off, this pin connected to the I
2
C-bus is floating and does not disturb the I
2
C lines.
[12] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.
[13] To minimize interference on the 12-bit ADC signal lines, do not configure the digital signal as output when using the 12-bit ADC. See
Table 187 .
To reduce interference from digital signals to the high-speed 12-bit ADC inputs, do not
configure digital pins that are pinned out close to the ADC signals as outputs when using
the 12-bit ADC. For the BGA256 package, the pins with interfering signals are shown in
Table 187 .
16.2.3 LPC436x/5x/3x/2x/1x, LPC43S6x/S5x/S3x Pin description
Remark: These parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of
ADC0 and ADC1 are combined in such a way that channel 0 inputs (named ADC0_0 and
ADC1_0) are tied together and connected to both, channel 0 on ADC0 and channel 0 on
ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are tied together and connected
to channel 1 on ADC0 and ADC1, and so forth. There are eight ADC channels total for the
two ADCs.
Table 187. 12-bit ADC signal interferences for BGA256 package
12-bit ADC signal LBGA256 Interfering pins LBGA256
ADCHS0 E3 P4_3, PC_0 C2, D4
ADCHS1 C3 P4_1, P8_0, PC_0 A1, E5, D4
ADCHS2 A4 PF_10, PF_11 A3, A2
ADCHS3 A5 PF_9, PF_10 D6, A3
ADCHS4 C6 P7_7, PB_6 B6, A6
ADCHS5 B3 PF_11 A2
ADCHS_NEG B5 P7_7, PF_8 B6, E6