UM10503
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User manual
Rev. 2.1 — 10 December 2015
995 of 1441
NXP Semiconductors
UM10503
Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with
The bits in this register select which events, if any, clear the STOP bit in the Control
register. (Since no events can occur when HALT is 1, only software can clear the HALT bit
by writing the Control register.)
31.3.7 SCT dither condition register
If UNIFY = 1 in the CONFIG register, only the L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
DITHER_L and DITHER_H. Both the L and H registers can be read or written individually
or in a single 32-bit read or write operation.
When the Dither Condition register contains all zeroes (the default value), the dither
engine advances to the next count in the dither pattern
every time
the SCT counter
reaches zero (i.e. at the start of every new SCT counter cycle).
It is possible, using this register, to alter that behavior by qualifying the advancement
through the dither pattern with designated events. As with the other condition/mask
registers (HALT, STOP, LIMIT, etc.) each bit in this register corresponds to an event.
Setting one or more of the bits in this register to ones will cause the dither engine to
advance to the next element in the dither pattern (i.e. increment the 16-state cycle
counter) only following SCT counter cycles during which one or more of the designated
dither events have occurred.
There is one, global Dither Condition register per 16-bit SCT. This register controls
advancement through the dither patterns for all of the match registers associated with that
half of the SCT.
For details on the dither engine and the dither pattern, see
Table 752. SCT start condition register (START, address 0x4000 0014) bit description
Bit
Symbol
Description
Reset
value
15:0
STARTMSK_L
If bit n is one, event n clears the STOP_L bit in the CTRL
register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15).
0
31:16 STARTMSK_H
If bit n is one, event n clears the STOP_H bit in the CTRL
register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31).
0
