UM10503
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User manual
Rev. 2.1 — 10 December 2015
1011 of 1441
NXP Semiconductors
UM10503
Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with
31.3.29 SCT output clear registers 0 to 15
Each output n has one clear register that controls how events affect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.
31.4 Functional description
31.4.1 Fractional matches
The first 6 match registers may be configured to have a fractional portion to their match
values. Higher average resolution is achievable on the match registers with associated
fractional match register by using a dithering mechanism. The dither engine delays the
assertion of a match by one counter clock every n (0 to 15) out of 16 counter cycles. The
value of n is specified in the 4-bit FRACMAT register associated with each of the first six
match registers.
Dithering can be disabled on any of the match registers by loading all zeroes (the default
value) into its FRACMAT register.
31.4.1.1 Dithering
At the start of each new SCT counter cycle (i.e. when the counter counts-down to zero in
bi-directional mode or is cleared to zero by a limit event), the dither engine determines
which matches are to be delayed by one clock during the coming counter cycle. Delaying
the match effectively adds 1 to the designated match value when up-counting or subtracts
1 when down-counting, during that particular counter cycle.
For each dither-enabled match register, the value programmed in its associated
FRACMAT register specifies how many out of every 16 counter cycles its match is to be
delayed. An algorithm applied to the FRACMAT value distributes this number as evenly as
possible across the 16 counter cycles. This results in a unique dither pattern for each
match register (See
Table 775. SCT output set register 0 to 15 (OUT[0:15]_SET, address 0x4000 0500 (OUT0_SET)
to 0x4000 0578 (OUT15_SET)) bit description
Bit
Symbol
Description
Reset
value
15:0
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn =
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
0
31:16
-
Reserved
Table 776. SCT output clear register 0 to 15 (OUT[0:15]_CLR, address 0x4000 0504
(OUT0_CLR) to 0x4000 057C (OUT15_CLR)) bit description
Bit
Symbol
Description
Reset
value
15:0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn =
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
0
31:16
-
Reserved
