NXP Semiconductors LPC43Sxx, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 1012 of 1441
NXP Semiconductors
UM10503
Chapter 31: LPC43xx/LPC43Sxx State Configurable Timer (SCT) with
Additional control over the dithering process is provided to the user via a Dither Condition
(event-mask) register. Typically, the dither engine advances though the match dither
patterns at the start of every new SCT counter cycle. The Dither Condition register allows
the user to specify that advancement to the next element in the dither patterns will only
occur if one or more designated events occurred during the previous cycle of the counter.
The dither algorithm is designed to spread out the cycles in which the matches are
delayed as evenly as possible across the 16 counter cycles. The following table shows the
dither pattern that is applied for each value of FRACMAT. A ‘D’ indicates the counter
cycles where a match on the relevant match register is delayed.
31.4.2 Alternate addressing for match/capture registers
The Match, Reload, Fractional match, Fractional match reload, Capture, and Capture
Control registers are arranged as consecutive words, with the standard division of each
word into two halfwords. When the UNIFY bit is zero, these two halfwords are related to
the L and H counters. Software has the option of writing words initially to set up both
halves of the SCT simultaneously, or writing halfwords to set up each half separately.
Applications can use a DMA controller to write Reload registers or to read Capture
registers. However, when UNIFY is 0, the addressing of the halfword registers is not
compatible with the requirement of many DMA controllers to use consecutive addresses
for sequential address operation.
Table 778 shows how the second half of the range
occupied by each type of register contains an alternate address map for halfword
accesses to the same registers, which is compatible with DMA that use sequential
address operation. When UNIFY is 1, perform DMA word accesses using standard
offsets.
Table 777. Dither pattern
Counter cycle
FRACMAT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0x0 - - - - - - - - - - - - - - - -
0x1 - - - - - - - - D - - - - - - -
0x2 - - - - D - - - - - - - D - - -
0x3 - - - - D - - - D - - - D - - -
0x4 - - D - - - D - - - D - - - D -
0x5 - - D - - - D - D - D - - - D -
0x6 - - D - D - D - - - D - D - D -
0x7 - - D - D - D - D - D - D - D -
0x8 - D - D - D - D - D - D - D - D
0x9 - D - D - D - D D D - D - D - D
0xA - D - D D D - D - D - D D D - D
0xB - D - D D D - D D D - D D D - D
0xC - D D D - D D D - D D D - D D D
0xD - D D D - D D D D D D D - D D D
0xE - D D D D D D D - D D D D D D D
0xF - D D D D D D D D D D D D D D D