UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1032 of 1441
NXP Semiconductors
UM10503
Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3
32.7 Functional description
32.7.1 Example timer operation
shows a timer configured to reset the count and generate an interrupt on
match. The prescaler is set to 2 and the match register set to 6. At the end of the timer
cycle where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
32.7.2 DMA operation
DMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits of
each timer. In order to have an effect, the GPDMA must be configured and the relevant
timer DMA request selected as a DMA source via the CREG block, see
When a timer is initially set up to generate a DMA request, the request may already be
asserted before a match condition occurs. An initial DMA request may be avoided by
having software by write a one to the interrupt flag location, as if clearing a timer interrupt.
See
. A DMA request will be cleared automatically when it is acted upon by
the GPDMA controller.
Fig 109. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.
PCLK
prescale
counter
interrupt
timer
counter
timer counter
reset
2
2
2
2
0
0
0
0
1
1
1
1
4
5
6
0
1
Fig 110. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabled
PCLK
prescale counter
interrupt
timer counter
TCR[0]
(counter enable)
2
2
0
0
1
4
5
6
1
0
