UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
658 of 1441
NXP Semiconductors
UM10503
Chapter 25: LPC43xx/LPC43Sxx USB0 Host/Device/OTG controller
25.6.5 USB Interrupt register (USBINTR)
The software interrupts are enabled with this register. An interrupt is generated when a bit
is set and the corresponding interrupt is active. The USB Status register (USBSTS) still
shows interrupt sources even if they are disabled by the USBINTR register, allowing
polling of interrupt events by the software. All interrupts must be acknowledged by
software by clearing (that is writing a 1 to) the corresponding bit in the USBSTS register.
25.6.5.1 Device mode
19
UPI
USB host periodic interrupt (USBHSTPERINT)
0
R/WC
0
This bit is cleared by software writing a one to it.
1
This bit is set by the Host Controller when the cause of an interrupt is a
completion of a USB transaction where the Transfer Descriptor (TD) has an
interrupt on complete (IOC) bit set
and
the TD was from the periodic
schedule. This bit is also set by the Host Controller when a short packet is
detected
and
the packet is on the periodic schedule. A short packet is
when the actual number of bytes received was less than the expected
number of bytes.
31:20
-
Table 473. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description
…continued
Bit
Symbol
Value
Description
Reset
value
Access
Table 474. USB Interrupt register in device mode (USBINTR_D - address 0x4000 6148) bit description
Bit
Symbol Description
Reset
value
Access
0
UE
USB interrupt enable
When this bit is one, and the USBINT bit in the USBSTS register is one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBINT bit in USBSTS.
0
R/W
1
UEE
USB error interrupt enable
When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS
register.
0
R/W
2
PCE
Port change detect enable
When this bit is a one, and the Port Change Detect bit in the USBSTS register is a
one, the host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Port Change Detect bit in USBSTS.
0
R/W
3
-
Not used by the Device controller.
4
SEE
System Error Enable
When this bit is a one, and the System Error bit in the USBSTS register is a one, the
host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the System Error bit in USBSTS register.
0
-
5
-
Not used by the Device controller.
6
URE
USB reset enable
When this bit is a one, and the USB Reset Received bit in the USBSTS register is a
one, the device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the USB Reset Received bit.
0
R/W
