UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
181 of 1441
NXP Semiconductors
UM10503
Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)
13.6.4 PLL0AUDIO registers
The PLL0AUDIO provides a wide range of frequencies for audio applications and can be
connected to multiple base clocks. The PLL0AUDIO can be used with or without a
fractional divider.
See
for instructions on how to set up the PLL0.
13.6.4.1 PLL0AUDIO status register
13.6.4.2 PLL0AUDIO control register
Table 132. PLL0AUDIO status register (PLL0AUDIO_STAT, address 0x4005 002C) bit
description
Bit
Symbol
Description
Reset
value
Access
0
LOCK
PLL0 lock indicator
0
R
1
FR
PLL0 free running indicator
0
R
31:2
-
Reserved
-
Table 133. PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit
description
Bit
Symbol
Value
Description
Reset
value
Access
0
PD
PLL0 power down
1
R/W
0
PLL0 enabled
1
PLL0 powered down
1
BYPASS
Input clock bypass control
1
R/W
0
CCO clock sent to post-dividers. Use this
in normal operation.
1
PLL0 input clock sent to post-dividers
(default).
2
DIRECTI
PLL0 direct input
0
R/W
3
DIRECTO
PLL0 direct output
0
R/W
4
CLKEN
PLL0 clock enable
0
R/W
5
-
Reserved
-
-
6
FRM
Free running mode
0
R/W
7
-
Reserved
0
R/W
8
-
Reserved. Reads as zero. Do not write
one to this register.
0
R/W
9
-
Reserved. Reads as zero. Do not write
one to this register.
0
R/W
10
-
Reserved. Reads as zero. Do not write
one to this register.
0
R/W
11
AUTOBLOCK
Block clock automatically during frequency
change
0
R/W
0
Disabled. Autoblocking disabled
1
Enabled. Autoblocking enabled
