UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
630 of 1441
NXP Semiconductors
UM10503
Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)
24.6.2 SPIFI command register
The Command Register may only be written as a word, but bytes, halfwords, and words
may be read from it. It may be written to when the CMD and MCINIT bits in the Status
register are 0, and under these circumstances writing initiates the transmission of a new
command. For a command that contains an address and/or intermediate data, software
should write to the Address and/or Intermediate Data registers, before writing to this
register. If the command contains output data, software should write it to the Data Register
after writing to this register. If the command contains input data, software can read it from
the Data Register after writing to this register.
26:24 -
Reserved.
-
27
PRFTCH_DIS
Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit
disables prefetching of cache lines.
0
0
Enable. Cache prefetching enabled.
1
Disable. Disables prefetching of cache lines.
28
DUAL
Select dual protocol.
0
0
Quad protocol. This protocol uses IO3:0.
1
Dual protocol. This protocol uses IO1:0.
29
RFCLK
Select active clock edge for input data.
0
0
Rising edge. Read data is sampled on rising edges on the clock, as in classic
SPI operation.
1
Falling edge. Read data is sampled on falling edges of the clock, allowing a
full serial clock of of time in order to maximize the serial clock frequency.
Remark:
MODE3, RFCLK, and FBCLK should not all be 1, because in this
case there is no final falling edge on SCK on which to sample the last data bit
of the frame.
30
FBCLK
Feedback clock select.
1
0
Internal clock. The SPIFI samples read data using an internal clock.
1
Feedback clock. Read data is sampled using a feedback clock from the SCK
pin. This allows slightly more time for each received bit.
Remark:
MODE3, RFCLK, and FBCLK should not all be 1, because in this
case there is no final falling edge on SCK on which to sample the last data bit
of the frame.
31
DMAEN
A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit
only when a DMA channel is used to transfer data in peripheral mode. Do not
set this bit when a DMA channel is used for memory-to-memory transfers
from the SPIFI memory area. DRQEN should only be used in Command
mode.
0
Table 448. SPIFI control register (CTRL, address 0x4000 3000) bit description
Bit
Symbol
Value Description
Reset
value
