NXP Semiconductors LPC43Sxx, User Manual

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User manual Rev. 2.1 — 10 December 2015 1328 of 1441
NXP Semiconductors
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Chapter 47: LPC43xx/LPC43Sxx 10-bit ADC0/1
47.6 Register description
The register addresses for the ADC0 are shown in Table 1112
Table 1111. ADC pin description
Pin
function Type Description
ADC0_[7:0]/
ADC1_[7:0] Input Shared Analog Inputs. The A/D converter cell can measure the voltage
on any of these input signals. The inputs are shared between ADC0 and
ADC1 on analog-only pins
Remark: The ADC0 pin is shared with the DAC0 pin.
ADC0_[6:0] Input Analog inputs.Inputs from multiplexed analog/digital pins to ADC0. The
A/D converter cell can measure the voltage on any of these input signals.
These pins are shared with ADC1.
ADC1_[7:0] Input Analog inputs.Inputs from multiplexed analog/digital pins to ADC1. The
A/D converter cell can measure the voltage on any of these input signals.
These pins are shared with ADC0.
ADCTRIG0 Input Trigger inputs to the ADC0/1.
ADCTRIG1 Input Trigger inputs to the ADC0/1.
VDDA Power Analog Power. Also voltage reference VREF for both ADCs.
VSSA Ground Analog ground.
Table 1112. Register overview: ADC0 (base address 0x400E 3000)
Name Access Address
offset
Description Reset
value
[1]
Reference
CR R/W 0x000 A/D Control Register. The AD0CR register must be written to
select the operating mode before A/D conversion can occur. 0x0000 0000 Table 1114
GDR R0 0x004 A/D Global Data Register. Contains the result of the most
recent A/D conversion. - Table 1115
- - 0x008 Reserved. -
INTEN R/W 0x00C A/D Interrupt Enable Register. This register contains enable
bits that allow the DONE flag of each A/D channel to be
included or excluded from contributing to the generation of
an A/D interrupt. 0x0000 0100 Table 1116
DR0 RO 0x010 A/D Channel 0 Data Register. This register contains the
result of the most recent conversion completed on channel 0 - Table 1117
DR1 RO 0x014 A/D Channel 1 Data Register. This register contains the
result of the most recent conversion completed on channel 1. - Table 1117
DR2 RO 0x018 A/D Channel 2 Data Register. This register contains the
result of the most recent conversion completed on channel 2. - Table 1117
DR3 RO 0x01C A/D Channel 3 Data Register. This register contains the
result of the most recent conversion completed on channel 3. - Table 1117
DR4 RO 0x020 A/D Channel 4 Data Register. This register contains the
result of the most recent conversion completed on channel 4. - Table 1117
DR5 RO 0x024 A/D Channel 5 Data Register. This register contains the
result of the most recent conversion completed on channel 5. - Table 1117