UM10503
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User manual
Rev. 2.1 — 10 December 2015
1367 of 1441
NXP Semiconductors
UM10503
Chapter 50: LPC43xx/LPC43Sxx EEPROM memory
50.5.2 Interrupt registers
These registers control interrupts from the EEPROM.
50.5.2.1 Interrupt enable clear register
50.5.2.2 Interrupt enable set register
50.5.2.3 Interrupt status register
Table 1165.Interrupt enable clear register (INTENCLR, address 0x4000 EFD8) bit description
Bits
Symbol
Description
Reset value
1:0
-
Reserved. Read value is undefined, only zero should be written.
NA
2
PROG_CLR_EN
Clear program operation finished interrupt enable bit for EEPROM.
0 = leave corresponding bit unchanged.
1 = clear corresponding bit.
0
31:3
-
Reserved. Read value is undefined, only zero should be written.
NA
Table 1166.Interrupt enable set register (INTENSET, address 0x4000 EFDC) bit description
Bits
Symbol
Description
Reset value
1:0
-
Reserved. Read value is undefined, only zero should be written.
NA
2
PROG_SET_EN
Set program operation finished interrupt enable bit for EEPROM device 1.
0 = leave corresponding bit unchanged.
1 = set corresponding bit.
0
31:3
-
Reserved. Read value is undefined, only zero should be written.
NA
Table 1167.Interrupt status register (INTSTAT, address 0x4000 EFE0) bit description
Bits
Symbol
Description
Reset
value
1:0
-
Reserved. The value read from a reserved bit is not defined.
NA
2
END_OF_PROG
EEPROM program operation finished interrupt status bit.
Bit is:
- set when this operation has finished OR when one is written to the corresponding bit
of the INTSTATSET register.
- cleared when one is written to the corresponding bit of the INTSTATCLR register.
0
31:3
-
Reserved. The value read from a reserved bit is not defined.
NA
