UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1232 of 1441
45.1 How to read this chapter
The C_CAN0/1 controllers are available on all LPC43xx/LPC43Sxx parts.
45.2 Basic configuration
The C_CAN is configured as follows:
•
See
for clocking and power control.
•
The C_CAN0 is reset by the CAN0_RST (reset # 55).
•
The C_CAN1 is reset by the CAN1_RST (reset # 56).
•
The ORed C_CAN0 and C_CAN1 interrupt is connected to slot # 12 in the Event
router.
•
The C_CAN0 interrupt is connected to interrupt #51 in the NVIC.
•
The C_CAN1 interrupt is connected to interrupt #43 in the NVIC.
•
Set the CAN clock divider CLKDIV to divide the CLK_APB3_CAN0 and
CLK_APB1_CAN1 clocks to run at less than 50 MHz. See
.
•
See
for calculating the CAN bit rate.
Remark:
The clocks to the C_CAN0 and C_CAN1 interfaces can be set independently of
each other.
Remark:
Use of C_CAN controller excludes operation of all other peripherals connected
to the same bus bridge. See the
LPC43xx errata
.
45.3 Features
•
Conforms to protocol version 2.0 parts A and B.
•
Supports bit rate of up to 1 Mbit/s.
•
Supports 32 Message Objects.
•
Each Message Object has its own identifier mask.
UM10503
Chapter 45: LPC43xx/LPC43Sxx C_CAN
Rev. 2.1 — 10 December 2015
User manual
Table 1032.C_CAN clocking and power control
Base clock
Branch clock
Operating
frequency
Clock to the C_CAN0 register interface
and C_CAN0 peripheral clock (PCLK).
PCLK must be divided by the CAN0
clock divider CLKDIV to be less than
50 MHz.
BASE_APB3_CLK
CLK_APB3_CAN0
up to
204 MHz
Clock to the C_CAN1 register interface
and C_CAN1 peripheral clock (PCLK).
PCLK must be divided by the CAN1
clock divider CLKDIV to be less than
50 MHz.
BASE_APB1_CLK
CLK_APB1_CAN1
up to
204 MHz
