UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
542 of 1441
22.1 How to read this chapter
The SD/MMC card interface is available on all LPC43xx/LPC43Sxx parts.
22.2 Basic configuration
The SD/MMC interface is configured as follows:
•
The SD/MMC is reset by the SDIO_RST (reset # 20).
•
The delay values on the sample and drive inputs and outputs can be adjusted using
the SDDELAY register in the SYSCON block. See
.
22.3 Features
The SD/MMC card interface supports the following features:
•
Secure Digital memory protocol commands.
•
Secure Digital I/O protocol commands.
•
Multimedia Card protocol commands.
•
CE-ATA digital protocol commands.
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Command Completion signal and interrupt to processor.
•
Completion Signal disable feature.
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One SD or MMC (4.4) or CE-ATA (1.1) device.
•
CRC generation and error detection.
•
Provides individual clock control to selectively turn ON or OFF clock to the card.
•
SDIO interrupts in 1-bit and 4-bit modes.
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SDIO suspend and resume operation.
•
SDIO read wait.
•
Block size of 1 to 65,535 bytes
•
FIFO over-run and under-run prevention by stopping card clock.
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Little-endian mode of AHB operation.
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Internal (bus mastering) DMA.
•
Two FIFOs, TX and RX FIFO (FIFO depth = 32 and FIFO data width = 32 bits).
UM10503
Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface
Rev. 2.1 — 10 December 2015
User manual
Table 355. SDIO clocking and power control
Base clock
Branch clock
Operating frequency
SDIO register
interface
BASE_M4_CLK
CLK_M4_SDIO
up to 204 MHz
SDIO bit rate clock
BASE_SDIO_CLK
CLK_SDIO
Up to 52 MHz
