UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1114 of 1441
NXP Semiconductors
UM10503
Chapter 39: LPC43xx/LPC43Sxx Event monitor/recorder
29:24 -
Reserved. Read value is undefined, only zero should be written.
NA
31:30 ERMODE
Controls enabling the Event Monitor/Recorder and selecting its operating
frequency. Event Monitor/Recorder registers can always be written to regardless
of the state of these bits. Events occurring during the 1-sec interval immediately
following enabling of the clocks may not be recognized.
0
0x0
Disable Event Monitor/Recorder clocks.
Operation of the Event Monitor/Recorder is disabled except for asynchronous
clearing of GP registers if selected.
0x1
16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample
clock for event input edge detection and glitch suppression.
Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out.
0x2
64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample
clock for event input edge detection and glitch suppression.
Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out.
0x3
1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample
clock for event input edge detection and glitch suppression.
Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out.
Table 917. Event Monitor/Recorder Control Register (ERCONTRO, address 0x4004 6084) bit description
Bit
Symbol
Value
Description
Reset
value
