NXP Semiconductors LPC43Sxx, User Manual

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User manual Rev. 2.1 — 10 December 2015 594 of 1441
23.1 How to read this chapter
The EMC is available on all LPC43xx/LPC43Sxx parts.
The memory and address bus widths depend on package size (see Table 410 ).
23.2 Basic configuration
The External Memory Controller is configured as follows:
•
See Table 411 for clocking and power control. Two clocks are supported:
– BASE_M4_CLK
– 1/2

BASE_M4_CLK
If the EMC clock EMC_CCLK is configured for 1/2

BASE_M4_CLK, the
CLK_M4_EMC_DIV branch clock must be configured for half-frequency clock
operation in both the CREG6 register (
Table 105 ) and the CCU1
CLK_EMCDIV_CFG register ( Table 164 ).
•
All four EMC_CLK clock signals must be configured for all SDRAM devices
independently of their size by selecting the EMC_CLK function and enabling the input
buffer (EZI = 1) in all four SFSCLKn registers in the SCU.
•
The EMC is reset by the EMC_RST (reset # 21).
UM10503
Chapter 23: LPC43xx/LPC43Sxx External Memory Controller
(EMC)
Rev. 2.1 — 10 December 2015 User manual
Table 410. EMC pinout for different packages
Function LBGA256 TFBGA180 TFBGA100 LQFP208 LQFP144 LQFP100
A EMC_A[23:0] EMC_A[23:0] EMC_A[13:0] EMC_A[23:0] EMC_A[15:0] -
D EMC_D[31:0] EMC_D[15:0] EMC_D[7:0] EMC_D[15:0] EMC_D[15:0] -
BLS EMC_BLS[3:0] EMC_BLS[3:0] EMC_BLS0 EMC_BLS[1:0] EMC_BLS[1:0] -
CS EMC_CS[3:0] EMC_CS[3:0] EMC_CS0 EMC_CS[3:0] EMC_CS[1:0] -
OE EMC_OE EMC_OE EMC_OE EMC_OE EMC_OE -
WE EMC_WE EMC_WE EMC_WE EMC_WE EMC_WE -
CKEOUT EMC_
CKEOUT[3:0] EMC_
CKEOUT[1:0] EMC_
CKEOUT[1:0] EMC_
CKEOUT[1:0] EMC_
CKEOUT[1:0] -
CLK EMC_CLK[3:0];
EMC_CLK01,
EMC_CLK23 EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23 EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23 EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23 EMC_CLK0,
EMC_CLK3;
EMC_CLK01,
EMC_CLK23 -
DQMOUT EMC_
DQMOUT[3:0] EMC_
DQMOUT[1:0] - EMC_
DQMOUT[1:0] EMC_
DQMOUT[1:0] -
DYCS EMC_
DYCS[3:0] EMC_DYCS[1:0] EMC_DYCS[1:0] EMC_DYCS[2:0] EMC_DYCS[1:0] -
CAS EMC_CAS EMC_CAS EMC_CAS EMC_CAS EMC_CAS -
RAS EMC_RAS EMC_RAS EMC_RAS EMC_RAS EMC_RAS -